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Amazon · 12 hours ago

Lead ASIC Implementation Engineer, Amazon Leo's DBF Silicon

Redmond, Washington, USA

Full-time

Onsite

Senior Level, Lead/Staff

$159K/yr - $215K/yr

7+ years exp

Amazon is a leading global technology company known for its innovative solutions. The Lead ASIC Implementation Engineer will be responsible for defining and implementing digital chip SOCs for communications via Low Earth Orbit satellites, ensuring seamless integration and performance of the chips.

Artificial Intelligence (AI)DeliveryE-CommerceFoundational AIRetail

No H1B

U.S. Citizen Only

Responsibilities

As the implementation lead you will set up the flow for both logic and physical synthesis flow for various technology nodes

Work with the ASIC design and DFT teams to understand the design and create timing constraints

Check the RTL design for clean synthesis run, perform STA and LEC on netlist

Work with RFIC teams to make sure the top level integration of analog blocks are done properly and correct by construction, including formal connectivity checks

Work with P&R teams to ensure a smooth hand off of netlists, ensure the timely execution of the P&R responsibilities by that team

Participate in flow reviews of all the blocks with the P&R team to ensure that they achieve the best PPA for all blocks

Lead the timing sign-off for the post P&R database

Ensure that the chip meets the required DFM criteria by verifying the IR/EM results

Qualification

ASIC implementationSynthesisStatic Timing Analysis (STA)Physical Design (P&R)Power gatingMethodology developmentLow power design (UPF)Team leadershipWritten communicationVerbal communicationMulti-team collaboration

Required

Bachelor's degree in Electrical Engineering or a related field

7+ years of experience in ASIC implementation, i.e., synthesis, STA and working with P&R for deep sub-micron nodes, preferably 16nm or smaller

Experience leading or solely developing the methodology and scripts for physical synthesis

Proven track record in taping out chips that have gone in to high volume production

Familiar with implementing chips that have multiple power islands and power gating

Preferred

Master's degree or Ph.D. degree in Electrical Engineering or related field

10+ years of experience in ASIC implementation

Experience in leading physical design

Strong exposure to UPF flow for low power design

Strong written and verbal skills

Experience of working in multi-site/multi-team environment

Benefits

Health insurance (medical, dental, vision, prescription, Basic Life & AD&D insurance and option for Supplemental life plans, EAP, Mental Health Support, Medical Advice Line, Flexible Spending Accounts, Adoption and Surrogacy Reimbursement coverage)

401(k) matching

Paid time off

Parental leave