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Intel Corporation · 2 hours ago

Sr. STA Engineer

United States

Full-time

Remote

Senior Level

$164K/yr - $269K/yr

7+ years exp

Intel Corporation is a leading technology company committed to innovation and smart device connectivity. They are seeking a highly skilled Sr. STA Engineer to join their full-chip timing team, responsible for achieving top-level timing closure for complex SoC/ASIC designs and ensuring timing accuracy and automation across the full chip.

Semiconductors

Growth Opportunities

No H1B

Responsibilities

Run and maintain top-level timing analysis across all modes and corners using tools like Primetime

Ensure every path is timed correctly; track and improve timing quality metrics such as coverage, margin distribution, and skew

Maintain and update STA tool versions and patch releases

Seamlessly roll out PVT corner changes and scaling methods for unsupported libraries

Develop robust scripts (Tcl, Python, shell) to automate STA runs, report generation, ECO flows, and environment setup

Create scalable and reusable infrastructure for timing tasks

Implement scaling techniques for missing libraries

Rapidly adjust PVT corners and integrate changes into the flow

Work closely with timing owners and block teams to resolve cross-boundary timing issues

Provide infrastructure and tooling support to timing owners

Ensure timing signoff criteria are met across all corners and modes

Validate timing post-ECO and post-layout

Work closely with the clocking team and other backend full chip designers for clocking balance, timing fixes, power delivery, and partitioning

Collaborate with architecture, clocking design, and logic design teams to deliver flow development for chip integration and validates high performance low power clock network guidelines

Qualification

Static Timing AnalysisSTA signoff toolsScripting (Tcl/Python)RTL Design DevelopmentPVT cornersTiming ECOsTiming automationProblem-solving skillsCommunication skillsCollaboration abilities

Required

Bachelors in Electrical Engineering, Computer Engineering, or STEM field with 9+ years or Masters Electrical Engineering, Computer Engineering, or STEM field & 6+ years or PhD Electrical Engineering, Computer Engineering, or STEM field & 4+ years of industry experience

7+ years of industry experience in Complex CPU/SOC/ASIC/FPGA implementation and timing closure

5+ years in STA signoff tools like Prime Time, Constraint generation and verification tool like Fishtail

3+ years scripting skills in TCL/Python/Perl/Shell

3+ years of RTL Design Development and physical implementation