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AMD · 9 hours ago

Memory Subsystem Design Verification Engineer

Austin, TX

Full-time

Onsite

Mid Level

$192K/yr - $289K/yr

AMD is a leading company focused on building innovative products that enhance computing experiences. The Memory Subsystem team is seeking Verification Engineers to design and develop high-speed memory subsystem solutions, emphasizing verification across multiple product lines and pre-silicon production-level firmware co-verification.

AI InfrastructureArtificial Intelligence (AI)Cloud ComputingComputerEmbedded SystemsGPUHardwareSemiconductor

Growth Opportunities

No H1B

Responsibilities

Proficiency in C/C++, System Verilog, UVM (object-oriented design), and scripting languages (e.g., Python, shell)

Experience in IP and subsystem verification with System Verilog/UVM and VCS

Background in testbench architecture, microarchitecture, and co-verification with firmware

Knowledge of code and functional coverage and how test plans map to cover goals

Ability to design and debug co-verification environments for production-level firmware

Experience developing transactor-based stimulus and maintaining test suites as features evolve

Ability to learn new toolsets/frameworks and contribute updates

Qualification

System VerilogUVMC/C++IP verificationTestbench architectureCo-verificationPythonScripting languagesDebuggingGitPerforceCollaborationAdaptabilityDocumentation

Required

Proficiency in C/C++, System Verilog, UVM (object-oriented design), and scripting languages (e.g., Python, shell)

Experience in IP and subsystem verification with System Verilog/UVM and VCS

Background in testbench architecture, microarchitecture, and co-verification with firmware

Knowledge of code and functional coverage and how test plans map to cover goals

Ability to design and debug co-verification environments for production-level firmware

Experience developing transactor-based stimulus and maintaining test suites as features evolve

Ability to learn new toolsets/frameworks and contribute updates

Bachelors or master's in electrical engineering, Computer Engineering, Computer Science, or a related field or equivalent practical experience in verification engineering

Preferred

Experience building monitors/checkers and developing SVA/OVL and synthesizable assertions

Verification experience with DDR/JEDEC standard IP, DDR PHY, or Memory Controllers

Experience verifying subsystems/components and applying methodologies to achieve subsystem verification

Familiarity with architectural models and SystemC

Experience with Zebu emulation for verification and debug

Firmware/hardware co-verification using UVM System Verilog, C-DPI, and gasket‑structured testbenches

Memory VIP integration, bring-up, and debug

End-to-end verification experience from front-end through lab bring-up

Understanding of synchronization techniques (e.g., handshakes, message passing) and hardware-level clocking, including multi-domain simulation synchronization

Experience with Git and Perforce

Managing regressions and coverage databases

SoC IP knowledge and a high-level understanding of the role and interfaces of each IP