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Samsung Ads · 13 hours ago

Lead Micro-Architect, Memory Controller

3655 N 1st St, San Jose, CA, USA

Full-time

Onsite

Lead/Staff

$222K/yr - $365K/yr

16+ years exp

Samsung, a world leader in advanced semiconductor technology, is seeking a highly skilled Lead Memory Controller Micro-Architect to lead the design and development of advanced memory controllers. This role involves ownership over the entire memory-controller micro-architecture and collaboration with cross-functional teams to ensure design functionality and achieve performance goals.

Marketing & Advertising

Responsibilities

You will assume ownership and exert significant influence over the entire memory-controller micro-architecture, including RTL design and performance/power optimization

You will translate innovative concepts into cutting-edge, next-generation memory technologies that drive Samsung's leadership in the field

You are the domain expert in technical areas with strong engineering foundation and RTL design experience, driving micro-architecture, RTL design, debug, and timing closure for custom memory controllers

You're passionate about microarchitecture development, from high-level exploration to delivering high-quality RTL on schedule, meeting performance, power, and area (PPA) goals

You ensure design quality through LINT, CDC, ECO flows, power analysis, and other methodologies

You collaborate with cross-functional teams to ensure design functionality, achieve PPA goals, and resolve implementation challenges in a fast-paced environment

You take ownership of deliverables by adhering to JEDEC standards, collaborating on SOC IP delivery, and applying knowledge of DDR PHY to ensure timely and accurate results

Qualification

Memory controller micro-architectureRTL designVerilogASIC design flowMemory technologiesJEDEC standardsScripting languagesCommunication skillsCollaboration skillsProblem-solving skills

Required

20+ years of experience with a Bachelor's Degree in Computer Science/Engineering, or 18+ years of experience with a Master's Degree, or 16+ years of experience with a PhD

Proven experience in memory controller micro-architecture and RTL design, owning all sub-blocks of custom memory controller designs

Deep expertise in multiple memory technologies, such as LPDDR4/5/6, PIM, DDR, GDDR, and HBM

Strong knowledge of JEDEC memory standards and working knowledge of DDR PHY

Demonstrated success in driving architecture through RTL design for high-performance digital systems

Strong expertise in Verilog and ASIC design flow, including RTL design, verification, synthesis, timing analysis, and ECO

Proficiency in scripting languages (Perl, Python) to support design and automation

Strong communication and collaboration skills; Ability to navigate ambiguity in a fast-paced, global team environment

Self-driven, curious, and passionate about logic design and innovation