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AMD · 20 hours ago

ASIC/RTL Design Engineer

San Jose, CA

Full-time

Onsite

Senior Level

$160K/yr - $240K/yr

AMD is a company focused on building innovative products that enhance computing experiences across various domains. They are seeking a Senior ASIC/RTL Design Engineer to contribute to the development of large SoCs, responsible for RTL ownership and integration, as well as verifying timing constraints for intricate designs.

AI InfrastructureArtificial Intelligence (AI)Cloud ComputingComputerEmbedded SystemsGPUHardwareSemiconductor

Growth Opportunities

No H1B

Responsibilities

Responsible for RTL design and integration

The candidate is expected to contribute to all aspects of SoC design including chip definition, architecture development and modeling, development of micro-architectural specification, conversion of micro-architectural specifications to logic implementation, verification, emulation, debug, synthesis and timing closure

Responsible for the development of complex multi-mode / multi-corner timing constraints that are compatible for RTL and signoff

Lead the effort to maintain RTL quality metrics in complex, hierarchical designs, while automating the process for increased efficiency

Implement the pre-route timing checks and QoR clean up to eliminate timing constraints issues and ensure a quality handoff for STA (static timing analysis) checks

Collaborate with CAD on the development of pre-production synthesis (Design Compiler) and STA (Primetime) work flows

Require a blend of SDC expertise, proficiency in EDA tools, and Tcl based scripting abilities (in both EDA environment and standalone Linux Tcl shell scripts)

Continuously review and identify areas for process improvements and early issue detection during the design phase

Qualification

SDC expertiseEDA tool proficiencyTCL scriptingRTL designTiming constraintsAnalytical skillsProblem-solving skillsCommunication skillsCollaboration

Required

Extensive experience in SDC development and debugging

Familiar with enhancing various RTL quality metrics for complex, hierarchical designs

Ability to automate processes for increased efficiency

Proficiency in both front-end (RTL) processes and back-end (Synthesis and P&R) processes

High energy and excellent written and verbal communication skills

Structured and organized approach to work

Collaborative and focused on achieving team and organizational goals

Responsible for RTL design and integration

Contribute to all aspects of SoC design including chip definition, architecture development and modeling, development of micro-architectural specification, conversion of micro-architectural specifications to logic implementation, verification, emulation, debug, synthesis and timing closure

Responsible for the development of complex multi-mode / multi-corner timing constraints that are compatible for RTL and signoff

Lead the effort to maintain RTL quality metrics in complex, hierarchical designs

Implement the pre-route timing checks and QoR clean up to eliminate timing constraints issues and ensure a quality handoff for STA (static timing analysis) checks

Collaborate with CAD on the development of pre-production synthesis (Design Compiler) and STA (Primetime) work flows

Require a blend of SDC expertise, proficiency in EDA tools, and Tcl based scripting abilities (in both EDA environment and standalone Linux Tcl shell scripts)

Continuously review and identify areas for process improvements and early issue detection during the design phase

Bachelor's or Master's degree in Electrical Engineering or Computer Engineering