Altera · 4 hours ago
Design/DFT Physical Design Integration Lead
San Jose, California, United States
Full-time
Onsite
Senior Level, Lead/Staff
$178K/yr - $239K/yr
10+ years expAltera is a leader in programmable solutions, providing tools and technologies for innovation in various markets. They are seeking a Design/DFT Physical Design Integration Lead to drive design integration tasks and lead full-chip implementation efforts, collaborating across teams to enhance design efficiency and quality of results.
Enterprise SoftwareManufacturingSemiconductorSoftware
Responsibilities
Own and drive design integration tasks focusing on Design/DFT constraint integration
Own and drive full‑chip implementation from RTL to GDSII, including timing closure, power optimization, and physical verification
Collaborate with RTL, DFT, STA, and packaging teams to ensure seamless integration and convergence across domains
Develop and maintain automation scripts (Tcl, Python, Perl, etc.) to enhance productivity and flow robustness
Evaluate and integrate EDA tools and methodologies to improve design efficiency and QoR
Lead technical reviews and provide guidance to design teams on best practices and flow usage
Analyze design metrics and debug complex issues across the physical design flow
Drive innovation in physical design methodologies to meet aggressive PPA and schedule targets
Qualification
Required
BS/MS or PhD in Electrical Engineering, Computer Engineering, or a related field and 10+ years of experience in the following:
Experience in physical design implementation and flow development
Experience in Design Constraint (SDC) development, validation, and execution
Experience in ATPG implementation/validation, including constraints, implementations, validations, and clocking
Industry‑standard EDA tools (Synopsys, Cadence, Siemens)
Scripting in Tcl, Python, Perl, and Shell
Full‑chip implementation and tape‑out of complex SoCs or FPGAs
Timing, power, signal integrity, and physical verification
Preferred
Hands‑on experience with full ATPG/DFT turnkey flow beyond general PD domain (SDC generation, pre‑layout, RTL verification, post‑layout simulation, ATPG generation, post‑silicon ATPG bring‑up)
Experience with hierarchical design methodologies and physical IP integration
Familiarity with advanced process nodes
Knowledge of machine learning techniques applied to EDA flows is a plus
Prior experience in FPGA architecture or design is highly desirable
Benefits
Incentive opportunities that reward employees based on individual and company performance
Company
Altera
Altera provides programmable logic devices and design software for various applications. It is a sub-organization of Intel.
1001-5000 employees
H1B Sponsorship
Altera has a track record of offering H1B sponsorships. Please note that this does not
guarantee sponsorship for this specific role. Below presents additional info for your
reference. (Data Powered by US Department of Labor)
Distribution of Different Job Fields Receiving Sponsorship
Represents job field similar to this job
Trends of Total Sponsorships
2025 (67)
Funding
Current Stage
Public CompanyTotal Funding
unknown2025-04-14Acquired
1988-03-31IPO
Leadership Team
Raghib Hussain
Chief Executive Officer
Recent News
Business Wire
2025-11-25
2025-11-19
Company data provided by crunchbase