Intel Corporation · 1 day ago
Collateral Device Engineer
US, Oregon, Hillsboro
Full-time
Hybrid
Senior Level
$191K/yr - $269K/yr
7+ years expIntel Corporation is a leader in semiconductor manufacturing, and they are seeking a highly skilled and experienced device technologist. The role involves developing device collateral for foundry technology, collaborating with teams to refine design rules, and ensuring compliance in high-volume manufacturing.
Semiconductors
Responsibilities
Design and develop comprehensive device collateral including test chip architectures and product scribe line layouts to support technology characterization and monitoring
Collaborate with Technology Development teams to establish and refine design rules for newly developed device architectures and customize collateral to meet customer-specific requirements
Develop and manage design-rule waiver processes, ensuring proper documentation and risk assessment for customer applications
Create and optimize scribe line monitoring structures for yield enhancement and process control in high-volume manufacturing
Work with manufacturing teams to implement device collateral that meets specifications, yield targets, and provides robust process monitoring capabilities
Drive the development of standardized test chip methodologies and scribe line layouts that are compatible with Intel's existing manufacturing processes and platforms
Analyze device parametric data from test chips and scribe line structures to drive continuous improvement in device performance and manufacturability
Provide technical guidance on design rule compliance and waiver justifications to cross-functional teams and customers
Stay updated with industry trends in device collateral design, test methodologies, and design rule evolution to inform development strategies
Qualification
Required
Master's degree in Electrical Engineering, Physics, or related field with 7+ years of experience in CMOS device engineering with focus on test chip design and device collateral development
Demonstrated expertise in CMOS semiconductor device physics and test chip design for advanced transistor device architecture
Experience in scribe line layout design and process monitoring structure development
Proficiency in design rule development, validation, and waiver management processes
Strong understanding of DTCO skills including understanding of SRAM, Standard cells and be the key interface and bridge between Process Integration, Yield, Device and Design
Preferred
Ph.D. degree in Electrical Engineering, Physics, or related field with 5+ years of experience in CMOS device engineering and collateral development
Demonstrated experience with design of experiment (DOE) principles applied to device collateral optimization
Strong skills in data analysis, scripting, and statistical techniques for test chip data interpretation
Hands-on experience in advanced node test chip design and scribe line optimization for 3nm-16nm FinFETs and sub 3nm GAA FETs
Experience with design rule checker (DRC) development and physical verification flows
Experience in High-Volume Manufacturing environment with focus on yield monitoring and process control structures
Knowledge of statistical process control (SPC) and advanced data analytics for device collateral optimization
Knowledge of mask generation including Boolean/OPC
Benefits
Competitive pay
Stock bonuses
Health
Retirement
Vacation
Company
Intel Corporation
Our mission is to shape the future of technology to help create a better future for the entire world, that’s the power of Intel Inside.
10001+ employees
H1B Sponsorship
Intel Corporation has a track record of offering H1B sponsorships. Please note that this does not
guarantee sponsorship for this specific role. Below presents additional info for your
reference. (Data Powered by US Department of Labor)
Distribution of Different Job Fields Receiving Sponsorship
Represents job field similar to this job
Trends of Total Sponsorships
2025 (2793)
2024 (3717)
2023 (3576)
2022 (4811)
2021 (3359)
2020 (1174)
Funding
Current Stage
Late StageLeadership Team
Brea Watts, MFA
Communications Manager, CEO
Carol Bartz
CEO
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