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Synchron · 18 hours ago

Principal ASIC Engineer (San Diego, CA)

San Diego, California, United States

Full-time

Onsite

Senior Level, Lead/Staff

$175K/yr - $225K/yr

5+ years exp

Synchron is a neurotechnology company with a mission to deliver the first commercially scalable brain-computer interface for millions of people with paralysis. They are seeking an experienced Principal ASIC Engineer to own the architecture, specification, and delivery of their high-performance neural interface ASIC, collaborating closely with internal teams and external vendors throughout the development process.

Information TechnologyManufacturingMedicalMedical Device

No H1B

Responsibilities

Define long-term ASIC architecture and top-level specifications for high-density neural signal acquisition and processing

Set design standards for ASICs that may affect multiple product lines

Provide technical leadership and accountability for multiple project teams, guiding them through complex design and verification challenges

Oversee the entire design flow from RTL (Register-Transfer Level) implementation (using Verilog/SystemVerilog) through synthesis, timing analysis, and verification closure using methodologies like UVM (Universal Verification Methodology)

Work closely with system architects, physical design, software, firmware, and validation teams to ensure seamless integration and system-level performance

Act as the escalation point for high-risk technical issues, conducting root cause analysis and implementing corrective actions during pre-silicon and post-silicon validation and debug

Mentor senior and staff engineers, conduct design reviews, and recommend new tools and practices for continuous improvement in the ASIC design flow

Assist in interfacing with external ASIC vendors, managing project schedules and milestones, and balancing resource trade-offs across projects

Qualification

ASIC designVerilog/SystemVerilogElectronic Design AutomationLow-power design techniquesBiopotential signal designCircuitLayout techniquesMixed-signal designPythonPerlTclProblem-solvingLeadershipCommunication

Required

M.S. or Ph.D. in Electrical or Computer Engineering, or a related field

5-10+ years of experience in ASIC/SoC design and development, with at least one full ASIC development cycle from concept to silicon

Deep expertise in HDL (Hardware Description Languages) such as Verilog/VHDL and HVL (Hardware Verification Languages) like SystemVerilog

Proficiency with Electronic Design Automation (EDA) tools (e.g., Synopsys, Cadence, Mentor Graphics) for simulation, synthesis, and timing analysis

Strong knowledge of design principles including clock domain crossing (CDC), low-power design techniques, and Design for Testability (DFT)

Demonstrated ability to architect and optimize ASICs for ultra-low-power operation, including sub-µW/channel front-ends, low-leakage circuits, and efficient power domains

Experience designing for microvolt-level biopotential signals with excellent linearity, dynamic range, and noise performance

Understanding of circuit and layout techniques to achieve high electrical isolation and minimize crosstalk across thousands of parallel acquisition channels

Hands-on experience analyzing and mitigating coupling, ground bounce, and substrate noise in dense mixed-signal designs

Ability to work across analog, digital, and packaging boundaries to ensure signal fidelity from sensor to system output

Experience with scripting languages (Python, Perl, Tcl) for automation

Exceptional problem-solving, analytical, and data-driven decision-making skills

Strong leadership and communication skills, with the ability to articulate complex technical concepts to diverse audiences

Ability to work effectively in cross-functional, often global, teams