Sintegra Inc. · 14 hours ago
Design Verification Engineer
Santa Clara County, CA
Full-time
Onsite
Mid LevelSintegra Inc. is seeking a highly skilled Design Verification Engineer to join their SoC verification team. The role involves verifying complex SoCs and high-speed interfaces to ensure functional correctness and system-level robustness of next-generation silicon.
SemiconductorSoftware
Hiring Manager
Shiplu Das
Responsibilities
Develop and execute comprehensive verification plans for SoC and IP-level designs
Build SystemVerilog/UVM-based verification environments for complex interfaces and subsystems
Verify and debug UCIe die-to-die interconnects, including link training, protocol compliance, and error handling
Verify Ethernet MAC and PCS layers (1G/10G/25G/100G+), including packet flow, PHY interactions, and corner cases
Perform verification of PCIe Root-of-Trust (RoT) IP (e.g., Rambus), including:
Secure boot flows
Key management and authentication
PCIe protocol compliance and security features
Execute SoC-level integration verification, including interconnects, resets, clocks, power management, and coherency
Create constrained-random tests, assertions, and functional coverage
Analyze simulation failures, root-cause issues, and work closely with design, architecture, and firmware teams to resolve bugs
Support regression automation, coverage closure, and tape-out readiness
Qualification
Required
Hands-on experience verifying complex SoCs and high-speed interfaces, including UCIe, Ethernet MAC/PCS, and PCIe Root-of-Trust IPs
Develop and execute comprehensive verification plans for SoC and IP-level designs
Build SystemVerilog/UVM-based verification environments for complex interfaces and subsystems
Verify and debug UCIe die-to-die interconnects, including link training, protocol compliance, and error handling
Verify Ethernet MAC and PCS layers (1G/10G/25G/100G+), including packet flow, PHY interactions, and corner cases
Perform verification of PCIe Root-of-Trust (RoT) IP, including secure boot flows, key management and authentication, PCIe protocol compliance and security features
Execute SoC-level integration verification, including interconnects, resets, clocks, power management, and coherency
Create constrained-random tests, assertions, and functional coverage
Analyze simulation failures, root-cause issues, and work closely with design, architecture, and firmware teams to resolve bugs
Support regression automation, coverage closure, and tape-out readiness
Company
Sintegra Inc.
Backed by 25+ years of deep silicon expertise, Sintegra is the trusted chip design partner to both Fortune 500 leaders and fast-moving startups - from Google, Meta, and Nvidia to Celestial AI, Cerebras, and Rivos.
Founded in 1999
11-50 employees
H1B Sponsorship
Sintegra Inc. has a track record of offering H1B sponsorships. Please note that this does not
guarantee sponsorship for this specific role. Below presents additional info for your
reference. (Data Powered by US Department of Labor)
Distribution of Different Job Fields Receiving Sponsorship
Represents job field similar to this job
Trends of Total Sponsorships
2025 (18)
2024 (7)
2023 (4)
2022 (3)
2021 (2)
Funding
Current Stage
Early StageLeadership Team
Bharat G.
President & CEO
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