Manpower San Diego · 1 day ago
Staff Design Verification Engineer
San Diego, CA
Full-time
Onsite
Senior Level, Lead/Staff
$135K/yr - $168K/yr
5+ years expManpower San Diego is seeking a Staff Design Verification Engineer to join their design verification team. The role involves verifying high-speed mixed-signal IP designs and overseeing the complete design verification lifecycle, from system-level concept to post-silicon support.
Staffing & Recruiting
Responsibilities
Define pre-silicon and post-silicon test plans based on design specs and using applicable standards working closely with design team
Architect and develop the testbench using advanced verification methodology such as SystemVerilog/UVM, Analog/mixed signal simulation, Low power verification, Formal verification and Gate level simulation to ensure high design quality
Author assertions in SVA, develop testcases, coverage models, debug and ensure coverage closure
Work with digital design, analog circuit design, modeling, controller/subsystem, & SoC integration teams to complete the successful PHY level verification, integration into subsystem and SoC, and post-silicon validation
From scratch VIP development experience for Serdes controller + PHY is an additional plus
Qualification
Required
Define pre-silicon and post-silicon test plans based on design specs and using applicable standards working closely with design team
Architect and develop the testbench using advanced verification methodology such as SystemVerilog/UVM, Analog/mixed signal simulation, Low power verification, Formal verification and Gate level simulation to ensure high design quality
Author assertions in SVA, develop testcases, coverage models, debug and ensure coverage closure
Work with digital design, analog circuit design, modeling, controller/subsystem, & SoC integration teams to complete the successful PHY level verification, integration into subsystem and SoC, and post-silicon validation
From scratch VIP development experience for Serdes controller + PHY is an additional plus
Knowledge of a HVL methodology like SystemVerilog/UVM
Experience working with various ASIC simulation/formal tools such as VCS, Xcellium/NCsim, Modelsim/Questa, VCFormal, Jaspergold, 0In and others
Knowledge of standard protocols such as PCIe, USB, MIPI, LPDDR, etc
Master's/Bachelor's degree in Electrical Engineering, Computer Engineering, or related field
5 years ASIC design verification, or related work experience
Preferred
Experience with Low power design verification, Formal verification and Gate level simulation
Knowledge of standard protocols such as PCIe, USB, MIPI, LPDDR, etc
Experience in scripting languages (Python, or Perl)
Experience with mixed-signal IP design verification, such as USB, PCIe, CXL, C2C, D2D, MIPI, UFS, DDR, PLL, Data Convertors (DAC, ADC), or sensors
3+ years' experience in data management and analysis in Excel or other programs
Proficiency with Microsoft Office applications (including Word, Excel, PPT, MS Project, Visio), Excel automation
Familiar with SharePoint, Jira, Tableau or similar tools
Good Verbal/Written communication skills
Proactive, strong attention to detail, organizational and time management skills
Company
Manpower San Diego
Actively involved in public policy, workplace issues, and economic development.
1001-5000 employees
Funding
Current Stage
Late StageCompany data provided by crunchbase