General Dynamics Mission Systems · 2 days ago
Sr Advanced ASIC FPGA Verification Engineer
Scottsdale, AZ
Full-time
Hybrid
Senior Level, Lead/Staff
8+ years expGeneral Dynamics Mission Systems engineers a diverse portfolio of high technology solutions, products and services that enable customers to successfully execute missions across all domains of operation. They are seeking a Senior Advanced ASIC FPGA Verification Engineer responsible for the definition, design, verification, and documentation of ASIC and FPGA developments, including creating test plans and verifying results.
AerospaceBusiness Information SystemsInformation ServicesInformation TechnologyNational SecuritySensor
No H1B
Security Clearance RequiredU.S. Citizen Only
Responsibilities
Responsible for definition, design, verification and documentation for ASIC (Application Specific Integrated Circuit) and/or FPGA (Field Programmable Gate Array) developments
Determines architecture, system simulation and detailed design approach
Defines module interfaces and all aspects of device design and simulation
Creates test and simulation plans that establish functional criteria
Verifies test results and analyzes performance
May also review vendor capabilities and simulation tools
Participates in the improvement of the ASIC/FPGA organizational processes
Supports the generation of technical engineering products by using the appropriate standards, processes, procedures, and tools throughout the ASIC/FPGA development life cycle
May provide leadership and/or direction to lower level employees
Independently determines approach to solutions
Contributes to the completion of major programs and projects
Plans and executes project tasks for activities described above
Qualification
Required
Bachelor's degree in Electrical or Computer Engineering, or a related Science, Engineering, Technology or Mathematics field
8+ years of job-related experience, or a Master's degree plus 6 years of job-related experience
U.S. citizenship is required
Ability to obtain a TS/SCI clearance within a reasonable amount of time from date of hire
Preferred
Agile experience
In-depth experience using RTL simulation tools such as Siemens Mentor Graphics Questa or Modelsim tools or equivalent in a Linux Environment
In-depth knowledge of System Verilog object oriented programming and the Universal Verification Methodology (UVM)
Understands UVM Testbench Architectures
Comfortable using and developing UVM agents, bus functional models
Understands different types of coverage, usage of cover classes, cover points, etc
Experience with predictive testbench components, functional coverage and assertions
Experience with constrained random testing
Experience with the Register Abstraction Layer
Familiarity with requirements-based verification, requirement tracing, and developing requirement verification strategies etc
Experience with scripting languages such as Linux shell scripts, TCL, Python
Familiarity with using Formal Verification tools, code coverage, writing waivers etc
Familiarity with Questa Verification IP (QVIP)
Developing UVM testbenches for designs implemented in Xilinx devices with Xilinx IP and SoCs
AXI protocols, PCIe, Space Wire, and Ethernet interfaces
DSP functions and common signal processing components
Familiar with debugging FPGA/ASIC hardware and assisting with HW/SW integration
Continuous Integration features of GITLab
Company
General Dynamics Mission Systems
General Dynamics Mission Systems designs and delivers critical systems and products for defense and cybersecurity customers. It is a sub-organization of General Dynamics.
10001+ employees
Funding
Current Stage
Late StageLeadership Team
Bo Elam
VP and CFO
Scott Butler
Senior Vice President Program Execution
Recent News
Washington Technology
2026-01-17
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