NVIDIA · 1 week ago
Senior ASIC Timing Engineer
Westford, MA
Full-time
Onsite
Senior Level, Lead/Staff
$168K/yr - $264K/yr
8+ years expNVIDIA is a leader in AI computing and has been transforming computer graphics and accelerated computing for over 25 years. They are seeking a Senior ASIC Timing Engineer to drive physical design and timing of high-frequency and low-power DPUs and SoCs, optimizing design constraints and synthesis parameters for performance and power targets.
AI InfrastructureArtificial Intelligence (AI)Consumer ElectronicsFoundational AIGPUHardwareSoftwareVirtual Reality
Responsibilities
You will drive physical design and timing of high-frequency and low-power DPUs and SoCs at block level, chiplet level, and/or full chip level
Analyze and optimize design constraints and synthesis parameters to achieve performance, power, and area targets
Help in driving frontend and backend implementation from RTL to gds2, including synthesis, equivalence checking, floor-planning, timing constraints, timing and power convergence, and ECO implementation
Qualification
Required
BS (or equivalent experience) in Electrical or Computer Engineering with 8 years experience or MS with 4+ years experience in Synthesis and Timing
Hands-on experience in full-chip/sub-chip Static Timing Analysis (STA), timing constraints generation and management, and timing convergence
Expertise in analysis and fixing of timing paths through ECOs including crosstalk and noise analysis
Expertise in physical design and optimization e.g., placement, routing, cell sizing, buffering, logic restructuring, etc. to improve timing and power, along with a background in implementing them through ECOs
Background in logic synthesis and/or logical equivalence checking (LEC)
Expertise and in-depth knowledge of industry standard EDA tools (Synopsys PrimeTime or Cadence Tempus)
Proficiency in Python, Tcl and Make for automation and scripting tasks
Preferred
Background in domain specific STA and timing convergence, such as CPUs, GPUs or Network processor implementation or SOCs
Understanding of DFT logic and experience with DFT timing closure for various modes e.g., scan shift and capture, transition faults, BIST, etc
Knowledge of deep sub-micron technology and associated process variations effects, including modeling and converging considering process variations
Experience in methodology and/or flow development as well as automation
Benefits
Equity
Benefits
Company
NVIDIA
NVIDIA is a computing platform company operating at the intersection of graphics, HPC, and AI.
10001+ employees
H1B Sponsorship
NVIDIA has a track record of offering H1B sponsorships. Please note that this does not
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2025 (1877)
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2023 (976)
2022 (835)
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Funding
Current Stage
Public CompanyTotal Funding
$4.09BKey Investors
ARPA-EARK Investment ManagementSoftBank Vision Fund
2023-05-09Grant· $5M
2022-08-09Post Ipo Equity· $65M
2021-02-18Post Ipo Equity
Leadership Team
Jensen Huang
Founder and CEO
Michael Kagan
Chief Technology Officer
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