Cadence · 2 days ago
Senior Principal DFT Design Engineer
Austin, TX
Full-time
Onsite
Senior Level, Lead/Staff
10+ years expCadence is a company that hires and develops leaders and innovators in technology. They are looking for a Senior Principal DFT Design Engineer with extensive experience in Design for Test, focusing on various testing methodologies and tools to ensure high-quality digital designs.
AerospaceElectronic Design Automation (EDA)HardwareMobileSemiconductorSoftware
No H1B
U.S. Citizen Only
Responsibilities
Prior 10-20 years of professional experience in SoC/ASIC Digital Design with focus on Design for Test (DFT)
Should possess intimate knowledge of DFT insertion flows
Basic scan chain insertion using synthesis or other software tools
Experience in compression scan insertion, LBIST and other scan technologies
Intimate knowledge of memory build-in self-test (MBIST)
Expertise in Automatic Test Pattern Generation (ATPG) to achieve design test coverage goals
Debug and Analysis of failures to improve fault coverage
Verification of ATPG testbenches and debugging root cause of simulation mis-compares
Working knowledge of JTAG 1149.1/6, IEEE1500 and IEEE1687
Knowledge of timing analysis and equivalency checks would be added bonus
Ability to work in collaborative team environment
Prior experience with Cadence tools and flows is highly desirable
Should be able to finish DFT tasks independently
Strong problem-solving skills. Exhibit discipline, thoroughness, and methodical approach in solving problems
Ability to work with stakeholders across cross-functional teams – Architecture, Design, Internal and External Customers
Self-driven and committed individual who can work in a fast-paced project environment
Qualification
Required
US citizenship required
Prior 10-20 years of professional experience in SoC/ASIC Digital Design with focus on Design for Test (DFT)
Should possess intimate knowledge of DFT insertion flows
Basic scan chain insertion using synthesis or other software tools
Experience in compression scan insertion, LBIST and other scan technologies
Intimate knowledge of memory build-in self-test (MBIST)
Expertise in Automatic Test Pattern Generation (ATPG) to achieve design test coverage goals
Debug and Analysis of failures to improve fault coverage
Verification of ATPG testbenches and debugging root cause of simulation mis-compares
Working knowledge of JTAG 1149.1/6, IEEE1500 and IEEE1687
Ability to work in collaborative team environment
Should be able to finish DFT tasks independently
Strong problem-solving skills. Exhibit discipline, thoroughness, and methodical approach in solving problems
Ability to work with stakeholders across cross-functional teams – Architecture, Design, Internal and External Customers
Self-driven and committed individual who can work in a fast-paced project environment
Preferred
Prior experience with Cadence tools and flows is highly desirable
Knowledge of timing analysis and equivalency checks would be added bonus
Hands-on knowledge of synthesis, verification and debugging Verilog testbenches
Company
Cadence
Cadence is a market leader in AI and digital twins, pioneering the application of computational software to accelerate innovation in the engineering design of silicon to systems.
10001+ employees
Funding
Current Stage
Public CompanyTotal Funding
unknown1998-02-20IPO
Leadership Team
Paul Cunningham
Senior Vice President and General Manager
Tom Beckley
Senior Vice President - Strategic Technology Programs
Recent News
2026-01-17
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2026-01-16
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