Qualcomm · 6 hours ago
Staff/ Sr. Staff Design Verification Engineer - QGOV
San Diego, CA
Full-time
Onsite
Senior Level, Lead/Staff
$148K/yr - $246K/yr
5+ years expQualcomm Technologies, Inc. is a leading company in the field of engineering and technology. They are seeking a Staff/ Sr. Staff Design Verification Engineer to develop verification methodologies and test plans for hardware building blocks. The role involves owning end-to-end design verification tasks and exploring innovative methodologies to enhance test quality and efficiency.
Artificial Intelligence (AI)Generative AISoftwareTelecommunicationsWireless
No H1B
Security Clearance RequiredU.S. Citizen Only
Responsibilities
Familiarity with RTL design in Verilog and System Verilog
Develop verification methodology, ensuring scalable and portable environment across simulation and emulation
Develop test plan to verify Hardware building blocks, Design macros and Standard interfaces (PCIE, DDR, USB, I2C, SPI, etc)
Own end to end DV tasks from coding Test bench and test cases, write assertions, running simulations and achieving all coverage goals
Explore innovative DV methodologies (formal, simulation and emulation based) to continuously push the quality and efficiency of test benches
Develop verification methodology, ensuring scalable and portable environment across simulation and emulation
Develop and maintain emulation environment to collect metrics related to emulation environment
Need to be in San Diego full time, 5 days a week
Develop environment to run verification test cases, OS boot, performance benchmarks and other vectors
Design, develop, and maintain CAD infrastructure for silicon design teams enabling bring up, test and debug automations
Execute verification plans, including design bring-up, DV environment bring-up, regression enabling for all features under your care, debug of the test failures
Qualification
Required
5+ years of work experience with RTL/FPGA design (Verilog), embedded system architecture
5+ years of Design Verification, Emulation and Debug experience with simulation and emulation and prototyping flows
Relevant experience of 5+ yrs in any of the mentioned domain - Design/Verification/ Implementation
Bachelor's degree in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience
OR Master's degree in Science, Engineering, or related field and 5+ years of ASIC design, verification, validation, integration, or related work experience
OR PhD in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience
Preferred
Knowledge of communication protocols such as AXI4-x, DDRx, PCIe, etc
Strong System Verilog/UVM based verification skills & experience with assertion & coverage-based verification methodology
Good understanding of chip-level functional model building
Good understanding of OOP concepts Experience in HVL such as System Verilog, UVM/OVM & System C
Knowledge of Behavioral and Structural models and familiarity with simulation environments
Experience customizing and debugging make-based build flows and working with Xilinx's Vivado tools
Experience with cm tools such as Git and Gerrit
Experience in formal / static verification methodologies will be a plus
Experience with emulation platforms – Palladium, Zebu, Veloce, FPGAs
Experience with synthesizing and optimizing designs and verification components developed in synthesizable Verilog
Experience with C/C++ DPI transactors and monitors
Develop and maintain emulation environment to collect metrics related to emulation environment
Develop environment to run verification test cases, OS boot, performance benchmarks and other vectors
Design, develop, and maintain CAD infrastructure for silicon design teams enabling bring up, test and debug automations
Execute verification plans, including design bring-up, DV environment bring-up, regression enabling for all features under your care, debug of the test failures
Experience with debugging tools such as JTAG and lab test equipment such as logic analyzers, oscilloscopes, signal generators, etc
Experience with GLS, and scripting languages such as Perl, Python is a plus
Linux OS proficiency
Benefits
Competitive annual discretionary bonus program
Opportunity for annual RSU grants
Highly competitive benefits package
Company
Qualcomm
Qualcomm designs wireless technologies and semiconductors that power connectivity, communication, and smart devices.
10001+ employees
Funding
Current Stage
Public CompanyTotal Funding
$3.5M1991-12-20IPO
1988-01-01Undisclosed· $3.5M
Leadership Team
Cristiano Amon
President & CEO
I
Isaac Eteminan
CEO
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