Ayar Labs · 1 day ago
Sr. Staff Engineer, ASIC Design Automation - CAD
San Jose, CA
Full-time
Onsite
Senior Level, Lead/Staff
$170K/yr - $223K/yr
5+ years expAyar Labs is revolutionizing computing by moving data with light, and they are seeking a Senior Staff Engineer to lead design automation for their high-performance ASIC/SoC team. The role involves architecting and maintaining design automation methodologies, optimizing existing processes, and providing technical guidance to junior engineers.
AI InfrastructureArtificial Intelligence (AI)ComputerHardwareInformation TechnologySemiconductor
Responsibilities
Flow Architecture: Architect, develop, and deploy robust automated flows for Synthesis, Place and Route (P&R), Static Timing Analysis (STA), and Physical Verification using industry-standard tools (Cadence/Synopsys)
Methodology Development: Drive improvements in design methodologies, specifically for high-speed digital and mixed-signal integration, hierarchical design planning, and signoff, ensuring high reliability and ease of use
Tool Integration: Manage the installation, qualification, and regression testing of EDA tools and PDKs for advanced process nodes
PDK & Tech Files: Customize and maintain technology files (LEF, TF, MMMC setups, DRC/LVS decks) to ensure compatibility between digital (Innovus/ICC2) and custom (Virtuoso) environments
Automation: Develop advanced scripts and wrappers (Python, Tcl, Make) to streamline design execution, data management, and quality of results (QoR) tracking
Flow Optimization: Analyze and optimize flow performance to improve runtime, compute resource usage, and license efficiency; identify bottlenecks and implement software solutions
Support & Mentorship: Serve as the primary focal point for resolving complex tool/flow issues and provide technical guidance to junior engineers
Qualification
Required
BS or MS in Electrical Engineering, Computer Science, or related fields
5+ years of industry experience in Chip Design Automation
Expert proficiency in scripting and automation using Python, Tcl, C-shell, and Makefiles
Deep understanding of the complete ASIC physical design flow (Synthesis, P&R, CTS, Routing, STA, and Signoff)
Hands-on experience supporting major DEA tools (e.g., Cadence Innovus/Genus or Synopsys Fusion Compiler)
Experience managing PDKs and technology files for advanced process nodes (5nm or 3nm)
Proficiency with physical verification flows (Mentor Calibre, Synopsys IC Validator) and debugging rule deck issues
Experience with version control systems (Git, Perforce) and workload management
Preferred
Experience developing Mixed-Signal flows (OpenAccess interoperability), bridging Cadence Virtuoso and digital P&R tools
Experience with PDK development (P-cells, techfiles) or customizing DRC/LVS decks
Experience with 3DIC/Chiplet packaging methodologies and co-design flows
Background in photonics design automation or special custom circuit requirements
Proven ability to work with EDA vendors to track feature requests and debug software bugs
Company
Ayar Labs
Ayar Labs develops optical I/O solutions for large-scale AI workloads to accelerate data movement within AI systems.
51-200 employees
H1B Sponsorship
Ayar Labs has a track record of offering H1B sponsorships. Please note that this does not
guarantee sponsorship for this specific role. Below presents additional info for your
reference. (Data Powered by US Department of Labor)
Distribution of Different Job Fields Receiving Sponsorship
Represents job field similar to this job
Trends of Total Sponsorships
2025 (14)
2024 (2)
2023 (7)
2022 (4)
2021 (4)
2020 (2)
Funding
Current Stage
Late StageTotal Funding
$374.65MKey Investors
Capital TENBoardman Bay Capital ManagementLockheed Martin Ventures
2024-12-11Series D· $155M
2023-05-24Series C· $25M
2022-04-26Series C· $130M
Leadership Team
Mark Wade
President and CEO, Co-Founder
Alex Wright-Gladstein
Co-Founder and Advisor
Recent News
2026-01-18
2025-11-23
Company data provided by crunchbase