R-10060901 Senior Design Engineer (SoC RTL) jobs in United States
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NXP Semiconductors · 23 hours ago

R-10060901 Senior Design Engineer (SoC RTL)

NXP Semiconductors is a leader in secure connectivity solutions for embedded applications, driving innovation across various markets. They are seeking a Senior Design Engineer (SoC RTL) to build subsystems and integrate SoC RTL for various digital designs, collaborating closely with architecture and circuit designers.

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Hiring Manager
Denise D.
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Responsibilities

Building Subsystems and/or SoC RTL integration for Internal or Vendor driven IPs like ARM Cores, DDR, PCIe, Ethernet, DSP/AIML cores, GPU, VPU, MIPI-CSI, USB, Display Controller
Write Micro-Architecture and detailed design specification in close collaboration with architecture, circuit designers, DFT/Physical Design/Verification engineers
Provide high-quality RTL description, including assertions, for the design
Perform all aspects of the SoC design flow from high level design to Synthesis
Perform concept studies and provide direction in terms of performance, gate count and power for various digital designs
Contributing to improvements in Tools, Flows and Methodologies across global design community, interacting with global sites

Qualification

SoC RTL integrationRTL Sign off checksSynopsys VCSCadence RTL simulatorLogic SynthesisTiming ClosureISO26262 functional safetyCommunicationCreative problem-solvingTeam playerMentoring junior members

Required

MS or PhD in Electrical/Electronic/ Computer Engineering
Requires 8+ years of experience in high performance digital logic designs and SoC Integration using ARM Cores, Bus Protocols and Interconnects
Must have expertise on RTL Sign off checks (LINT, CDC, RDC, LEC, UPF)
Experience with Synopsys VCS or Cadence RTL simulator, Design Complier (DC) or RTL Compiler (RC or Genus), Verdi Debugging tool
Self-motivated with Excellent written and verbal communication skills
Creative problem-solving skills, logic analysis skills, ability to logically break complex problems down to manageable components
Should be a team player and willing to work with cross functional teams in issues resolution
Experience collaborating with international teams
Experience mentoring junior team members and overseeing their work

Preferred

Clock/Reset/Power Management Architecture would be a plus
Logic Synthesis and Timing Closure, Netlist ECO would be a plus
ISO26262 based functional safety relevant microcontroller architectures is a plus

Company

NXP Semiconductors

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NXP Semiconductors produces secure connectivity solutions for embedded applications.

Funding

Current Stage
Public Company
Total Funding
$2.56B
Key Investors
European Investment Bank
2025-08-12Post Ipo Debt· $1.5B
2025-01-15Post Ipo Debt· $1.06B
2010-08-06IPO

Leadership Team

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Bill Betz
Chief Financial Officer
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Andy Micallef
EVP Global Operations
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