Ayar Labs · 12 hours ago
Engineer, Physical Design
San Jose, CA
Full-time
Onsite
Entry, Mid Level
$120K/yr - $160K/yr
2+ years expAyar Labs is revolutionizing computing by moving data with light and is seeking a collaborative Physical Design Engineer to join their ASIC/SoC team. The role involves contributing to the development of next-generation electro-optical engines and complex mixed-signal designs, executing the full physical design flow, and collaborating with cross-functional teams.
AI InfrastructureArtificial Intelligence (AI)ComputerHardwareInformation TechnologySemiconductor
Responsibilities
Execute the full physical design flow (RTL2GDS) for digital and mixed-signal blocks, including floorplanning, power planning, placement, and routing
Perform Static Timing Analysis (STA) to identify setup/hold violations and implement ECOs to achieve timing convergence
Analyze clock structures and assist in optimizing clock distribution for skew and latency
Run and debug DRC, LVS, and Antenna checks using industry-standard verification tools to ensure manufacturing compliance
Participate in power optimization, including clock gating, power domain, and IR drop analysis
Develop and maintain Tcl/Python scripts to automate standard design tasks and improve flow efficiency
Partner with the RTL design and Custom Layout teams to resolve integration issues and ensure clean hand-offs
Qualification
Required
Bachelor's degree in Electrical/Computer Engineering (or related field) with 2+ years of industry experience in physical design OR Master's degree in Electrical/Computer Engineering (or related field) with 0-2 years of industry experience
Strong understanding of digital logic design and CMOS device physics
Familiarity with the ASIC design cycle, including Synthesis, P&R, STA, and Signoff
Hands-on experience (via work or academic projects) with industry-standard P&R tools (e.g., Cadence Innovus/Encounter, Synopsys ICC2/Fusion Compiler)
Proficiency in scripting languages (Tcl, Python, or Perl) for design automation and data parsing
Comfortable working in a Linux/Unix environment
Preferred
Experience or coursework in Advanced Process Nodes (7nm, 5nm, or smaller)
Prior internship or co-op experience in a Physical Design or Hardware Engineering role
Familiarity with physical verification tools such as Mentor Calibre or Synopsys IC Validator
Understanding of low-power design standards (UPF/CPF)
Knowledge of timing constraints (SDC), or signal integrity analysis
Experience with version control systems (e.g., Git, Perforce, Subversion)
Company
Ayar Labs
Ayar Labs develops optical I/O solutions for large-scale AI workloads to accelerate data movement within AI systems.
51-200 employees
H1B Sponsorship
Ayar Labs has a track record of offering H1B sponsorships. Please note that this does not
guarantee sponsorship for this specific role. Below presents additional info for your
reference. (Data Powered by US Department of Labor)
Distribution of Different Job Fields Receiving Sponsorship
Represents job field similar to this job
Trends of Total Sponsorships
2025 (14)
2024 (2)
2023 (7)
2022 (4)
2021 (4)
2020 (2)
Funding
Current Stage
Late StageTotal Funding
$374.65MKey Investors
Capital TENBoardman Bay Capital ManagementLockheed Martin Ventures
2024-12-11Series D· $155M
2023-05-24Series C· $25M
2022-04-26Series C· $130M
Leadership Team
Mark Wade
President and CEO, Co-Founder
Alex Wright-Gladstein
Co-Founder and Advisor
Recent News
2026-01-18
2025-11-23
Company data provided by crunchbase