Zettascale Computing Corp. · 9 hours ago
Founding Engineer - RTL/Architecture/FPGA
San Francisco, CA, US
Full-time
Onsite
Entry Level
$150K/yr - $300K/yr
1+ years expZettascale Computing Corp. is building the next generation of chips to power AI with their novel polymorphic architecture. They are seeking a Founding Engineer who will work across hardware-software boundaries to develop state-of-the-art AI compute engines and influence the future of AI compute.
Computer Hardware
Responsibilities
Work across architecture, verification, and physical design to hit PPA targets (area/power/perf)
Design compute datapaths and memory subsystems for AI accelerators, GPUs, or high-performance CPUs
Integrate high-speed interfaces/IP (PCIe, CXL, DDR/HBM, Ethernet, SerDes)
Implement DFT-aware RTL coding patterns and maintain reusable IP
Debug and triage failures from simulation/emulation, interpret waveforms, and drive root-cause closure with DV/PD
Proficiency with front-end toolchains and build/flow automation and tooling
Qualification
Required
Background in Electrical Engineering, Computer Engineering, or equivalent field
Strong digital design fundamentals (pipelining, clocking/reset strategy, latency/throughput tradeoffs, clean microarchitecture)
Strong foundation in mixed-signal & digital IC design (VLSI, semiconductor physics, RTL)
RTL quality discipline (lint, CDC/RDC, X-prop awareness, assertions/SVA, code review hygiene)
Synthesis/constraints expertise (SDC constraints, synthesis/PPA iteration, timing closure with physical design)
Debug expertise (triage failures from simulation/emulation, interpret waveforms, drive root-cause closure with DV/PD)
Proficiency with front-end toolchains (VCS/Xcelium/Questa, Verilator, SpyGlass-style linting, DC/Genus-class synthesis)
Build/flow automation and tooling (Python, Tcl, Nix)
Work across architecture, verification, and physical design to hit PPA targets (area/power/perf)
Preferred
Experience designing compute datapaths and memory subsystems for AI accelerators, GPUs, or high-performance CPUs (bandwidth/latency-driven design)
High-speed interface/IP integration experience (PCIe, CXL, DDR/HBM, Ethernet, SerDes)
DFT-aware RTL (scan-friendly coding patterns, test hooks, clean resets, well-defined clock gating strategy)
Experience writing/maintaining reusable IP (parameterization, clean bus protocols, well-structured interfaces)
5+ years (or equivalent) designing synthesizable RTL (SystemVerilog/Verilog) for ASICs and/or high-performance FPGA prototypes
Formal methods experience (property writing, bounded proofs) and/or post-silicon debug workflows
HW/SW boundary experience (drivers/firmware bring-up, performance counters, profiling, build systems)
Experience with systems programming (Linux kernel modules, low-level)
Experience with (Sci)ML frameworks (e.g., PyTorch, TinyGrad, JAX, Lux.jl)
Autodidactic polymath with a strong mathematical background
Someone who doesn't fret when faced with near-impossible technical challenges
Benefits
Highly competitive compensation
Significant equity
Company
Zettascale Computing Corp.
Energy efficient chips for AI YC S24
2-10 employees
Funding
Current Stage
Early StageCompany data provided by crunchbase