Zettascale Computing Corp. · 17 hours ago
Founding Engineer - Physical Design
San Francisco, CA, US
Full-time
Onsite
Mid Level
$150K/yr - $300K/yr
3+ years expZettascale Computing Corp. is building the next generation of chips to power AI. They are seeking a Founding Engineer in Physical Design to contribute to the development of their state-of-the-art AI compute engines, focusing on critical decisions that will influence the future of AI compute.
Computer Hardware
Qualification
Required
Background in Electrical Engineering, Computer Engineering, or equivalent field
Owned major RTL-to-GDSII steps (floorplanning, power planning, placement, CTS, routing, ECOs, timing closure)
Strong foundation in mixed-signal & digital IC design (VLSI, semiconductor physics, RTL)
Strong signoff fundamentals (STA setup/hold across corners, RC extraction, DRC/LVS/antenna/erc closure, tapeout readiness)
Proficiency with industry EDA flows/tools (Innovus/ICC2, PrimeTime, StarRC/Quantus, Calibre, OpenROAD)
Constraint and methodology expertise (SDC authoring/validation, MMMC setup, clocking strategy, clean handoffs with RTL)
Power integrity expertise (IR/EM analysis, power grid planning, practical mitigation tradeoffs)
Debug expertise (congestion/timing pathologies, routing-driven timing, crosstalk sensitivity, SI/PI interactions)
EDA flow automation and scripting (Tcl, Python, Nix)
3+ years of experience
Preferred
5+ years (or equivalent) hands-on digital/SoC physical design, with 1+ successful tapeout (ideally 7nm or smaller)
Advanced-node signoff experience (≤5nm) and modern variation methodology (OCV/AOCV, PVT/derates) with strong correlation discipline
Top-level integration experience across hierarchical blocks (abstracts, boundary timing, physical integration, chip-level routing strategy)
Experience with (Sci)ML frameworks (e.g., PyTorch, TinyGrad, JAX, Lux.jl)
Experience with systems programming (Linux kernel modules, low-level)
Autodidactic polymath with a strong mathematical background
Someone who doesn't fret when faced with near-impossible technical challenges
Benefits
Highly competitive compensation + significant equity
Company
Zettascale Computing Corp.
Energy efficient chips for AI YC S24
2-10 employees
Funding
Current Stage
Early StageCompany data provided by crunchbase