Achronix Semiconductor Corporation · 3 hours ago
Sr. Manager, ATE Test Development Engineer
Santa Clara, CA
Full-time
Onsite
Senior Level, Lead/Staff
10+ years expAchronix Semiconductor Corporation is a fabless semiconductor corporation based in Santa Clara, California, offering high-performance FPGA solutions. Achronix is seeking an experienced Senior Manager, Test Development Engineering to lead test program development, characterization, and production test strategies for FPGA integrated circuits.
3D TechnologyDeveloper APIsDeveloper ToolsField-Programmable Gate Array (FPGA)HardwareManufacturingSemiconductorSoftwareTechnical Support
Responsibilities
Develop, debug, and optimize ATE test programs on the Advantest V93000 (93K) test platform to validate FPGA functionality and performance
Utilize off-line tester tools and emulation environments to prepare and validate test flows before deployment on the ATE
Utilize efficient vector compression with multi-port vector capability for handling large pattern quantities with large vector depths
Own load-board/probe-card design and validation. Ensure test hardware meets performance, reliability, and cost targets
Define and execute comprehensive test plans tailored for FPGA architectures in collaboration with design, product, and DFT teams
Implement test methodologies to maximize coverage while optimizing cost, yield, and reliability
Handle and manipulate industry-standard test pattern formats, including WGL, VCD, EVCD, STIL. In depth understanding of WGL or STIL files and their function
Set up and validate functional, ATPG, MBIST, and high-speed loopback tests
Understand vector file structures, including cycle-based timing relationships, pin-level sequencing, and event-based triggers
Translate simulation patterns into 93K-compatible formats for FPGA functional verification
Debug and modify vector files directly on the ATE as needed for test pattern debug and optimization
Deep understanding of high-speed memory and serial interfaces such as SerDes, GDDR, and DDR test's function, purpose, and methodology
Utilize efficiently Advantest V93000 (93K) multi-port vectors
Commercial pattern conversion tool knowledge
Capability of understanding and writing software routines to develop custom test methods to extend ATE’s built-in capabilities to achieve specific test functions such as burning an efuse and digital capture
Write C++ based custom solutions for test automation and result analysis
Define characterization plans for complex high-power FPGA with the DFT team
Analyze process, voltage, and temperature (PVT) variations to assess device performance across environmental and manufacturing conditions, ensuring high-power FPGAs maintain timing, power, and functionality across all specified operating conditions
Define production test limits – Use characterization data to establish pass/fail criteria for high-volume manufacturing, preventing yield loss or excessive fallout by setting optimal test limits based on statistical analysis of device behavior
Identify performance bottlenecks, timing margin issues, and power-integrity failures through detailed characterization analysis, ATE-to-bench correlation by comparing tester results with bench validation measurements
Develop thermal management solution for device under test
ATE data processing and transformation – Extract, parse, and structure raw ATE data logs into readable formats such as Excel or SQL databases, ensuring efficient data organization for further analysis
Statistical analysis and data visualization – Perform statistical analysis to identify trends, outliers, and correlations, transforming raw test data into meaningful reports and visualizations enabling effective collaboration with design and product engineering teams
Optimize test limits, process parameters, and binning strategies for yield improvement
Understand the semiconductor production flow, from wafer fabrication, wafer sort, assembly, to package-level testing. Ensure test strategies align with process variations, yield optimization, and reliability requirements across different manufacturing stages
Integration of test strategies with manufacturing processes – Develop ATE test methodologies that account for fab process variations, back-end packaging challenges, and final test requirements. Collaborate with wafer foundries, outsourced semiconductor assembly and test (OSAT) partners, and supply chain partners to ensure smooth new product introduction (NPI) and high-volume production ramp-up
Analyze yield data to identify root causes of failures, implement corrective actions, and optimize test limits, process parameters, and binning strategies to improve overall production yield
Develop strategies to reduce test cost and optimize throughput without compromising quality
Minimize unnecessary test loops and refine test limits to improve efficiency
Implement parallel and multi-site testing to reduce test time
Understand package substrate design principles, including signal integrity, power delivery, and material selection
Identify and mitigate issues such as crosstalk, impedance mismatches, and warpage
Analyze thermal characteristics (θ JA , θ JC ), power dissipation, and cooling solutions to prevent thermal-induced failures
Execute reliability stress tests such as HTOL, HAST, TC, HTS ESD/LU testing to ensure device reliability
Develop burn-in strategies for high-power devices BIB design, and test pattern development
Assess device aging, failure mechanisms, and reliability under operational stress conditions
Understand burn-in oven and its features/design and how they apply to high-power devices
Qualification
Required
Strong analytical and problem-solving skills in test development, debugging, and failure analysis
Deep knowledge of integrated circuit fundamentals, device physics, and FPGA architecture
Experienced in ATE platforms, particularly Advantest V93000 (93K)
Understanding ATPG scan, MBIST, fuse and other structural and functional test methodologies
Understanding reliability stress testing, semiconductor manufacturing flows, and ATE-to-bench correlation
Proficiency in C++, Python, Perl, and data analytics tools (JMP, MATLAB, Excel, SQL, etc.)
10+ years of hands-on experience in semiconductor test engineering and product development
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related engineering field
Preferred
Proven ability to manage projects and execute test plans in a fast-paced semiconductor environment
Experience leading cross-functional teams and working in a startup-like, dynamic culture
Strong communication skills and ability to present technical data to both engineers and non-engineers
Demonstrated ability to work independently and manage ambiguity effectively
Company
Achronix Semiconductor Corporation
Achronix Semiconductor Corporation is a fabless semiconductor corporation based in Santa Clara, California, offering high-performance FPGA solutions.
51-200 employees
H1B Sponsorship
Achronix Semiconductor Corporation has a track record of offering H1B sponsorships. Please note that this does not
guarantee sponsorship for this specific role. Below presents additional info for your
reference. (Data Powered by US Department of Labor)
Distribution of Different Job Fields Receiving Sponsorship
Represents job field similar to this job
Trends of Total Sponsorships
2025 (5)
2024 (3)
2023 (16)
2022 (12)
2021 (6)
2020 (6)
Funding
Current Stage
Growth StageTotal Funding
$135.78MKey Investors
Argonaut Partners
2013-04-09Debt Financing· $3.53M
2012-08-01Series Unknown· $9.84M
2011-03-01Series C· $45M
Leadership Team
Robert Blake
Chief Executive Officer
Steve Mensor
VP of Marketing and Strategic Planning
Recent News
2025-07-29
2025-05-17
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