Qualcomm · 21 hours ago
High-speed Low-Power Interconnect Technology Sr. Engineer
Qualcomm Technologies, Inc. is seeking a highly skilled Senior Device Engineer with expertise in low‑power interconnects and SiPh/optical interfaces. The role involves collaboration with design, CAD, yield, and test teams to develop and implement low‑power, high‑density interconnect technologies for advanced memory ICs and chiplets.
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Responsibilities
Design and optimize low‑power chiplet‑to‑chiplet interconnects using copper (TSVs, micro‑bumps) and optical waveguides
Develop and simulate PIC components, including modulators, photodetectors, multiplexers, fiber‑to‑chip couplers, and lasers/uLED
Construct and validate optical link budgets, ensuring robust Tx/Rx signal integrity (IMDD/Coherent)
Perform optical/RF simulations using Ansys Lumerical (FDTD, MODE, INTERCONNECT), COMSOL, or similar tools
Build and apply AI‑based inverse design workflows to discover novel, high‑performance photonic or RF structures
Model and mitigate manufacturing‑induced variations and assess their impact on interconnect device performance for fab tape‑outs
Partner with test, yield, and design teams to address fab‑related issues for new optical/SiPh processes and products
Support technology benchmarking and model validation using test IP cores for PIC structures and interconnect Rx/Tx building blocks
Support end‑to‑end tape‑out activities including mask reviews, database preparation, and validation
Lead wafer‑ and die‑level optical characterization including automated probe station measurements of bandwidth, insertion loss, and thermal behavior
Interface with global CAD, design, SQE, YMT, package, and reliability teams to resolve issues effectively
Collaborate with external IP vendors, fabs, OSATs, and silicon/III‑V service partners to ensure timely execution
Qualification
Required
Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience
OR Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience
OR PhD in Science, Engineering, or related field
Preferred
Minimum 2 years of experience in silicon photonics, optics, high‑speed interconnects, or PIC design
Hands‑on experience with interconnect circuit design, PIC design/simulation, and PEX/EM tools (Cadence, ADS, Lumerical, COMSOL)
Knowledge of digital/RF/MSA CMOS design flows is a plus
Experience with technology development, benchmarking, and model validation using test IP for RF/PIC/analog applications
Strong understanding of interconnect link‑budget calculations, optical communications, and AI‑driven simulation workflows
Excellent communication skills with demonstrated ability to meet deadlines and solve problems efficiently
Experience with hardware description languages such as Verilog or VHDL
Experience using statistical tools and scripting languages (Python, Tcl, JMP)
Understanding of CMOS/SiPh process flows, including lithography, etch, and deposition
Knowledge of optical/SiPh process modules is a strong plus
Benefits
Competitive annual discretionary bonus program
Opportunity for annual RSU grants
Highly competitive benefits package
Company
Qualcomm
Qualcomm designs wireless technologies and semiconductors that power connectivity, communication, and smart devices.
H1B Sponsorship
Qualcomm has a track record of offering H1B sponsorships. Please note that this does not
guarantee sponsorship for this specific role. Below presents additional info for your
reference. (Data Powered by US Department of Labor)
Distribution of Different Job Fields Receiving Sponsorship
Represents job field similar to this job
Trends of Total Sponsorships
2025 (2013)
2024 (1910)
2023 (3216)
2022 (2885)
2021 (2104)
2020 (1181)
Funding
Current Stage
Public CompanyTotal Funding
$3.5M1991-12-20IPO
1988-01-01Undisclosed· $3.5M
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