Intellectt Inc · 1 week ago
Senior ASIC / RTL Design Engineer
Intellectt Inc is hiring a Senior ASIC / RTL Design Engineer for an onsite role in Texas. This position focuses on SoC-level RTL design, ownership of critical design blocks, and contribution to successful production tape-outs.
Responsibilities
Design and own RTL blocks for complex SoC designs
Develop micro-architecture and detailed design documentation
Collaborate with architecture, verification, and physical design teams through tape-out
Perform and resolve Lint, CDC, and RDC issues
Support synthesis, static timing analysis, and timing optimization
Participate in silicon bring-up and debug for owned features
Implement scripting and automation to improve design efficiency
Qualification
Required
5+ years of experience in ASIC / RTL design
Strong experience designing RTL blocks for SoC environments
Proven track record of multiple production ASIC tape-outs
Hands-on experience with Verilog / SystemVerilog
Experience with Lint, CDC, RDC, synthesis, and STA
Preferred
Experience with timing constraints and exceptions
Knowledge of low-power and power optimization techniques
Experience with ARM-based architectures
Familiarity with AXI, APB, or CHI protocols
Scripting experience using Python, Perl, or Tcl
Company
Intellectt Inc
Intellectt Inc.
Funding
Current Stage
Late StageCompany data provided by crunchbase