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Senior Mask Layout Engineer jobs in United States
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IonQ · 1 week ago

Senior Mask Layout Engineer

IonQ is developing the world's most powerful full-stack quantum computer based on trapped-ion technology. They are seeking a Senior Mask Layout Engineer to lead the tapeout process for quantum computers, working closely with cross-functional teams to enhance design and workflows.
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Responsibilities

Conduct Python-based layout for full-reticle tapeouts with commercial foundries
Develop and maintain internal component PCell and automated circuit layout libraries
Interface with designers, test engineers, packaging engineers, and foundry team to define layout rules and component designs
Implement physical verification checks of layouts, including DRC and LVS
Develop detailed documentation of tapeouts and lead layout reviews with other team members
Work with cross-functional teams to understand circuit requirements and make recommendations to improve design, layout, and test workflows

Qualification

Python-based mask layoutSemiconductor manufacturing knowledgePhysical verification DRCPhysical verification LVSAutomated circuit layout librariesCommercial simulation environmentsCommunication skillsAttention to detailIndependent work ability

Required

Bachelor's degree in Photonics, Physics, Electrical Engineering, or related field, or equivalent practical experience
Knowledge of semiconductor manufacturing processes and techniques
Excellent programming and software skills, including development in an IDE, proficiency with version control software, shell scripting, and code documentation
2+ years of experience with Python-based mask layout software packages such as Luceda IPKISS, GDSFactory, or Klayout
Conduct Python-based layout for full-reticle tapeouts with commercial foundries
Develop and maintain internal component PCell and automated circuit layout libraries
Interface with designers, test engineers, packaging engineers, and foundry team to define layout rules and component designs
Implement physical verification checks of layouts, including DRC and LVS
Develop detailed documentation of tapeouts and lead layout reviews with other team members
Work with cross-functional teams to understand circuit requirements and make recommendations to improve design, layout, and test workflows

Preferred

M.S. or Ph.D. in Photonics, Physics, Electrical Engineering, or related field
5+ years experience in generating layout files for complex semiconductor flows with custom elements, such as MEMS, integrated photonics, or superconducting circuits
Past ownership of full-reticle tapeouts with commercial foundries
Experience with commercial simulation, verification, and layout environments such as Synopsys, Cadence, and Ansys
Familiarity with photonic and/or analog electronic device principles including design, test, and fabrication
Proficiency in physical verification including DRC, LVS, and ERC
Experience with semiconductor and/or photonic workflows for tapeout with commercial foundries
Excellent verbal and written communication skills
A meticulous attention to detail and excellent track record of documenting requirements, implementation plan, and tracking progress
Ability to work independently, prioritizing tasks and managing time effectively in a deadline-oriented environment

Benefits

Comprehensive medical, dental, and vision plans
Matching 401K
Unlimited PTO and paid holidays
Parental/adoption leave
Legal insurance
A home internet stipend
Pet insurance

Company

IonQ

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IONQ offers enterprise-grade quantum systems designed for businesses seeking to harness the power of quantum computing in their operations.

Funding

Current Stage
Public Company
Total Funding
$3.8B
Key Investors
Heights Capital ManagementSamsung Catalyst FundCambium Capital Partners
2025-10-10Post Ipo Equity· $2B
2025-07-07Post Ipo Equity· $1B
2025-03-10Post Ipo Equity· $372.6M

Leadership Team

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Marco Pistoia
CEO, IonQ Italia
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Niccolo de Masi
Chairman & Chief Executive Officer
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Company data provided by crunchbase