Google · 17 hours ago
Design Technology Co-Optimization Engineer
Sunnyvale, CA
Full-time
Onsite
Entry, Mid Level
$132K/yr - $189K/yr
2+ years expGoogle is a leader in AI and Infrastructure technology, and they are seeking a Design Technology Co-Optimization Engineer to shape the future of AI/ML hardware acceleration. In this role, you will drive cutting-edge TPU technology and collaborate with various teams to optimize silicon solutions for datacenter-class applications.
AppsArtificial Intelligence (AI)Cloud StorageSearch EngineSEO
Responsibilities
Execute high-fidelity Place and Route (P&R) experiments to evaluate the PPA impact of advanced process features, library architectures, and design rule variations on datacenter-class IP
Drive Design Technology Co-Optimization (DTCO) by collaborating with foundries and internal technology teams to define optimal metal stacks, track heights, and scaling boosters (e.g., backside power delivery, buried power rails)
Quantify process entitlement through systematic benchmarking of logic and memory macros, identifying bottlenecks in power density and timing closure for next-generation nodes
Develop automated physical design methodologies and flows to accelerate technology pathfinding and enable rapid what-if analysis of emerging transistor architectures
Influence System Technology Co-Optimization (STCO) by partnering with Hardware Architects and Circuit Designers to translate process-level innovations into system-level performance gains
Qualification
Required
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience
2 years of experience in Physical Design (RTL-to-GDS) or Technology Development, focusing on advanced nodes (e.g. 7nm, 5nm, or below)
Experience in scripting and automation using Tcl and Python (or Perl) to manage design sweeps and data extraction
Experience with industry-standard Place and Route (P&R) tools and Static Timing Analysis (STA) tools
Experience in CMOS device physics, FinFET/nanosheet architectures, and the impact of layout parasitics on PPA
Preferred
Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture
Experience working with major foundry technology files (PDKs) and interpreting Design Rule Manuals (DRM) to guide physical implementation
Experience in Design Technology Co-Optimization (DTCO), including standard cell library characterization, metal stack optimization, and evaluation of scaling boosters (e.g., backside power delivery)
Experience with RTL synthesis and standard cell library optimization
Expertise in power integrity and reliability analysis and physical verification
Familiarity with datacenter-class IP blocks, such as high-performance CPU/GPU cores, SRAM arrays, or high-speed interconnects
Benefits
Bonus
Equity
Benefits
Company
Google specializes in internet-related services and products, including search, advertising, and software. It is a sub-organization of Alphabet.
10001+ employees
H1B Sponsorship
Google has a track record of offering H1B sponsorships. Please note that this does not
guarantee sponsorship for this specific role. Below presents additional info for your
reference. (Data Powered by US Department of Labor)
Distribution of Different Job Fields Receiving Sponsorship
Represents job field similar to this job
Trends of Total Sponsorships
2025 (8763)
2024 (8872)
2023 (9682)
2022 (11626)
2021 (9109)
2020 (9785)
Funding
Current Stage
Public CompanyTotal Funding
$26.1MKey Investors
Andy Bechtolsheim
2004-08-19IPO
1999-06-07Series Unknown· $25M
1998-11-01Angel· $1M
Leadership Team
Sundar Pichai
CEO
Thomas Kurian
CEO - Google Cloud
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