Google · 10 hours ago
TPU PCIe RTL Design Engineer
Sunnyvale, CA
Full-time
Onsite
Senior Level
$156K/yr - $229K/yr
5+ years expGoogle is a leading technology company focused on AI and machine learning innovations. They are seeking a TPU PCIe RTL Design Engineer to drive the development of high-performance PCIe subsystems and SoC infrastructure for their next-generation Tensor Processing Units, collaborating closely with software and hardware teams.
AppsArtificial Intelligence (AI)Cloud StorageSearch EngineSEO
Responsibilities
Lead the PCIe microarchitecture and RTL development, ensuring high-performance designs that strictly adhere to PPA targets, coding standards, and quality guidelines
Manage the full RTL lifecycle, including documentation and coding, while ensuring the design is sign-off ready for Lint, CDC, and synthesis
Partner with system architects to integrate the PCIe subsystem, ensuring it meets chip-level bandwidth, latency, and power consumption goals
Coordinate with Verification and Physical Design teams to develop test plans, leverage PCIe VIP, and achieve successful timing closure
Resolve complex protocol issues and lead post-silicon bring-up to ensure link integrity and subsystem performance
Qualification
Required
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience
5 years of experience in ASIC design, including one project focused on PCIe logic
Experience debugging RTL using Verdi/VCS and automating tasks via Python or Perl
Experience in SystemVerilog/Verilog for RTL development and microarchitecture definition
Experience with PCIe protocol layers (e.g., Transaction, Data Link, and Physical) or LTSSM
Experience with Clock Domain Crossing (CDC), timing closure, or synthesis flows
Preferred
Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture
8 years of ASIC design experience, including 3 years in PCIe (Gen4/5/6) controller or protocol logic
Knowledge of ASIC flow (DFT, synthesis, PnR), SerDes, and scripting (Python, Tcl, or Perl)
Advanced RTL design skills mastering multi-clock domains, timing closure, datapath optimization, and hardware/firmware partitioning
Expertise in PCIe architecture, including LTSSM, TLP/FLIT pipelines, flow control, ordering rules, and performance tuning
Proven cross-functional leadership, driving efforts with software/system teams from RTL development through silicon bring-up
Benefits
Bonus
Equity
Benefits
Company
Google specializes in internet-related services and products, including search, advertising, and software. It is a sub-organization of Alphabet.
10001+ employees
H1B Sponsorship
Google has a track record of offering H1B sponsorships. Please note that this does not
guarantee sponsorship for this specific role. Below presents additional info for your
reference. (Data Powered by US Department of Labor)
Distribution of Different Job Fields Receiving Sponsorship
Represents job field similar to this job
Trends of Total Sponsorships
2025 (8763)
2024 (8872)
2023 (9682)
2022 (11626)
2021 (9109)
2020 (9785)
Funding
Current Stage
Public CompanyTotal Funding
$26.1MKey Investors
Andy Bechtolsheim
2004-08-19IPO
1999-06-07Series Unknown· $25M
1998-11-01Angel· $1M
Leadership Team
Sundar Pichai
CEO
Thomas Kurian
CEO - Google Cloud
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