Senior ASIC Design Verification Engineer jobs in United States
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Talently · 14 hours ago

Senior ASIC Design Verification Engineer

Talently is a rapidly growing innovator in the technology industry, shaping the future of AI infrastructure. They are seeking a Senior ASIC Design Verification Engineer to lead verification planning and execution for ASIC designs, collaborating with cross-functional teams to ensure robust validation and innovate verification methodologies.

RecruitingStaffing Agency
Hiring Manager
Josh Wu
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Responsibilities

Lead comprehensive verification planning and execution for fabric-level and full-chip ASIC designs, ensuring robust validation across all design hierarchies
Collaborate cross-functionally with teams in architecture, firmware, and design to create and refine detailed test plans
Design and implement advanced testbenches using constrained random stimulus generation, intelligent checkers, scoreboards, and targeted assertions
Architect and execute verification strategies, including coverage analysis, automated regression management, and data-driven insights for high efficiency and quality
Drive verification best practices through structured code reviews, agile sprint planning, and systematic feature deployment processes
Innovate by researching and adopting next-generation methodologies, automated flows, and emerging technologies, such as AI-driven verification tools

Qualification

ASIC Design VerificationSystemVerilog/UVMChip-level ValidationC/C++ ProgrammingTest Planning

Required

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related technical field
7-10+ years of hands-on ASIC/SoC design verification experience, including test plan development, simulation environment creation, and complex debugging
Expertise in fabric-level and chip-level verification methodologies and best practices
Advanced proficiency with SystemVerilog/Verilog, UVM, and C/C++ programming, including embedded code for RISC-based processors
Proven ability to create scalable verification flows and frameworks, and implement coverage-driven, assertion-based verification strategies

Preferred

Experience with automated verification flows and AI-driven verification tools
Background in deploying verification environments for inference chiplets or AI hardware
Familiarity with advanced regression management and coverage analysis tools
Strong cross-functional communication skills and previous exposure to fast-paced, agile engineering environments
Knowledge of systematic feature deployment and best practices in verification documentation

Company

Talently

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Funding

Current Stage
Early Stage
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