Acceler8 Talent · 7 hours ago
Principal Physical Design Engineer
Acceler8 Talent is partnering with a well-funded startup to hire multiple experienced Physical Design Engineers. This team is focused on building the next-generation compute platform for companies developing GenAI models, where you will own large portions of verification execution at the subsystem and chip-level of a high-performance data center chip.
Responsibilities
Help define and refine verification methodologies that scale from individual blocks to subsystems, full-chip environments, and system-level validation
Take ownership of verification activities at the subsystem and chip levels, developing testbenches, test suites, and supporting infrastructure to achieve both functional and structural coverage goals
Lead the planning and execution of verification reviews, including test plan assessments, progress updates, and closure evaluations, ensuring readiness for key silicon milestones such as design freeze and tapeout
Qualification
Required
Proven end-to-end verification experience, taking designs from architectural or specification-level definition all the way through to production silicon
Proficiency in SystemVerilog along with scripting and programming languages such as Python, C/C++, Bluespec, or similar tools used for verification and silicon modeling
Demonstrated use of modern verification frameworks including UVM and assertion-based methods; strong skills in both formal and simulation-based verification are essential
Experience developing reusable tests, drivers, and infrastructure that can transition seamlessly into silicon validation and post-silicon debug workflows
Solid understanding of microarchitecture and design principles for high-performance compute systems (CPUs, GPUs, accelerators), high-speed interconnects, memory subsystems, and related components
Familiarity with emulation and FPGA prototyping environments is beneficial
Hands-on involvement in silicon bring-up and debug is considered a strong plus