SpanIdea Systems · 15 hours ago
DFT Engineer
San Francisco Bay Area
Contract
Onsite
Senior Level
5+ years expSpanIdea Systems is seeking an experienced Design-for-Test (DFT) Contractor to support the testing and validation of next-generation semiconductor SoCs. This role involves working closely with Front-End and Physical Design teams to implement robust DFT and test solutions for RF and Bluetooth/Wireless LAN product lines.
AutomotiveInternet of Things
Hiring Manager
Ahmed Faraaz
Responsibilities
Design, implement, and validate DFT architectures for advanced SoC designs
Develop, debug, and optimize Memory BIST using Siemens Tessent flows
Perform gate-level simulations and resolve simulation issues
Create and maintain automation scripts using Tcl, Perl, and Python
Implement scan compression techniques (SEQ, Ultra, TestKompress)
Generate ATPG patterns using Tetramax
Support ATPG diagnosis, ATE debug, and silicon bring-up activities
Perform DFT pattern translation using VTRAN
Work with RTL designs using Verilog/SystemVerilog
Apply basic STA and timing analysis concepts using PrimeTime , including:
CDC checks
Clock gating
Timing constraints
Qualification
Required
5+ years of hands-on industry experience in Design-for-Test (DFT)
Strong analytical, problem-solving, and debugging skills
Proven ability to work independently and deliver high-quality results with minimal supervision
Company
SpanIdea Systems
Spanidea is a global technology company delivering state-of-the-art engineering and digital solutions.
1001-5000 employees
H1B Sponsorship
SpanIdea Systems has a track record of offering H1B sponsorships. Please note that this does not
guarantee sponsorship for this specific role. Below presents additional info for your
reference. (Data Powered by US Department of Labor)
Distribution of Different Job Fields Receiving Sponsorship
Represents job field similar to this job
Trends of Total Sponsorships
2024 (1)
2020 (1)
Funding
Current Stage
Late StageRecent News
Company data provided by crunchbase