SBT · 12 hours ago
Lead Static Timing Analysis Engineer (STA)
San Francisco Bay Area
Full-time
Hybrid
Lead/Staff
10+ years expSBT is an executive recruiting firm for a confidential company seeking a hands-on technical STA lead. The role involves collaborating with systems HW engineers and SW architects to develop cutting-edge computing systems and solving complex challenges in chip development.
RecruitingStaffing Agency
Hiring Manager
Justin Kinsey
Responsibilities
Perform static timing analysis (STA) on digital circuits to ensure timing closure and identify timing-related issues
Develop and maintain STA scripts and tools to automate timing analysis and reporting
Collaborate with design teams to identify and resolve timing-related issues, including clock domain crossing, metastability, and setup/hold violations
Develop and maintain timing models and constraints for complex digital circuits
Optimize timing performance by analyzing and optimizing clock tree, flip-flop placement, and routing
Work closely with physical design engineers to ensure timing constraints are met during the physical design phase
Qualification
Required
10+ years of industry experience is required
Proven experience with STA signoff constraint authoring for full-chip level, tapeout signoff requirements, checklists, and associated automation
Expertise in various static timing tools (e.g., PrimeTime, Tempus)
Preferred
Master's degree is preferred
Company
SBT
Leaders in the semiconductor industry know that recruiting people with specialized skills in a competitive global market is a significant challenge.
2-10 employees
Funding
Current Stage
Early StageLeadership Team
Justin Kinsey
Executive Vice President and Chief Strategy Officer
Recent News
2024-01-30
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