Altera · 7 hours ago
Senior Design Verification Engineer
San Jose, California, United States
Full-time
Onsite
Senior Level, Lead/Staff
$179K/yr - $235K/yr
10+ years expAltera is at the forefront of enabling the future of advanced semiconductor solutions. As a Senior Design Verification Engineer, you will lead the development and execution of comprehensive verification plans for complex digital ASIC/FPGA designs, mentor junior engineers, and collaborate with cross-functional teams to enhance verification processes.
Enterprise SoftwareManufacturingSemiconductorSoftware
Responsibilities
Lead the development and execution of comprehensive verification plans for complex digital ASIC/FPGA designs
Define and implement robust verification strategies using industry-standard methodologies (e.g., UVM, SystemVerilog)
Build high-quality, reusable verification IP and testbench environments
Analyze functional coverage and testbench metrics to drive closure and quality
Debug design and verification issues alongside architects, RTL designers, and implementation teams
Mentor and guide junior verification engineers and contribute to best practices across the team
Collaborate with cross-functional partners to accelerate verification throughput and support product release goals
Drive continuous improvement of verification flows and automation
Qualification
Required
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related technical field
10+ years of professional Design Verification experience in ASIC/FPGA environments
7+ years of hands-on experience with SystemVerilog for testbench and verification development
5+ years of experience using UVM (Universal Verification Methodology) in production verification environments
5+ years of experience with simulation tools (e.g., Synopsys VCS, Cadence Xcelium, Mentor Questa)
3+ years of experience with coverage-driven verification and functional coverage closure
Experience with industry-standard scripting languages such as Python, Perl, or TCL (3+ years)
Ability to debug complex RTL/design issues using simulation and waveform analysis (5+ years)
Strong written and verbal communication skills, with experience documenting verification plans and results (5+ years)
Preferred
Advanced degree (Master's or Ph.D.) in Electrical/Computer Engineering or equivalent
Experience with formal verification tools (e.g., JasperGold, OneSpin)
Experience with hardware emulation/prototyping platforms
Familiarity with Version Control Systems (e.g., Git) and CI/CD flows for verification automation
Prior mentorship or team leadership experience
Knowledge of high-speed interfaces (e.g., PCIe, Ethernet, DDR) verification
Exposure to Python-based verification frameworks and automation flows
Benefits
Incentive opportunities that reward employees based on individual and company performance
Company
Altera
Altera provides programmable logic devices and design software for various applications. It is a sub-organization of Intel.
1001-5000 employees
H1B Sponsorship
Altera has a track record of offering H1B sponsorships. Please note that this does not
guarantee sponsorship for this specific role. Below presents additional info for your
reference. (Data Powered by US Department of Labor)
Distribution of Different Job Fields Receiving Sponsorship
Represents job field similar to this job
Trends of Total Sponsorships
2025 (67)
Funding
Current Stage
Public CompanyTotal Funding
unknown2025-04-14Acquired
1988-03-31IPO
Leadership Team
Raghib Hussain
Chief Executive Officer
Recent News
Business Wire
2025-11-25
2025-11-19
Company data provided by crunchbase