Technika Search · 1 day ago
ASIC Engineer
San Diego, CA
Full-time
Hybrid
Senior Level, Lead/Staff
10+ years expTechnika Search is seeking an ASIC Engineer who will be responsible for designing ASIC and FPGA used in cellular products. The role involves collaboration with engineering teams on architecture, system validation, and supporting ASIC/FPGA development efforts.
Staffing & Recruiting
Hiring Manager
Jill Martinelli
Responsibilities
Verification and validation for our products’ ASIC and FPGA
Support other teams during the development of products
Be proactive and identify problems early
Deliver on schedule
Qualification
Required
The ASIC Engineer will be responsible for designing ASIC and FPGA used in cellular products
You will be highly collaborative with other engineering teams (software, hardware and system) on architecture and system validation
Responsible for supporting our ASIC/FPGA development effort including FPGA synthesis, Timing constraints, ASIC backend support, FPGA low level tests on prototyping platform
Verification and validation for our products' ASIC and FPGA
Support other teams during the development of products
Be proactive and identify problems early
Deliver on schedule
Experience with the following tools: System Verilog
Experience with Perl, awk or sed scripting
Experience with GIT version control system
Experience with Cadence simulator, linter and code coverage
Experience with Intel FPGA tools (Quartus)
Experience with Quartus Platform Designer and DDR memory interface
Experience with Oscilloscope
Experience with ASIC timing analysis tool (Prime Time or other)
Basic knowledge of C language, for the purpose of writing test code for ASIC and FPGA validation
Good scripting capability with Perl, Awk, sed etc.…
In depth experience with ASIC timing constraints (sdc)
In depth experience with ASIC timing analysis
Experience with ASIC simulation, Cadence XCELIUM preferably
Ability to work in a fast-paced environment
Excellent verbal and written communication skills
Foster a professional attitude and demonstrate integrity and flexibility
Entrepreneurial, rapid learner, inquisitive, and persistent
Excellent organizational skills and attention to detail
Ability to efficiently use video conferencing tools to manage interactive meetings and webinars as needed
Minimum of 10 to 15 years of ASIC & FPGA design
Proven successful experience completing multiple ASIC tape-out, preferably as a technical chip leader
Proven successful experience completing multiple FPGA designs for ASIC prototyping and products
Experience working with other teams (software, hardware, and systems)
Minimum Bachelor's, Engineering, or other similar degree
Preferred
Nice to have: High speed transceivers interfaces such as CPRI or JESD204B
Nice to have: DDR4/DDR5 experience
Arria 10 FPGA experience preferable
Company
Technika Search
Technical and Executive Search Firm
2-10 employees
Funding
Current Stage
Early StageLeadership Team
Jill Martinelli
Executive Recruiter/CEO
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