Cynet Systems · 3 months ago
FPGA/ASIC Design Engineer
Cynet Systems is a company seeking an ASIC/FPGA Design Engineer responsible for developing, implementing, and verifying high-performance communications and networking ASIC/FPGA products. The role includes architecture design, RTL coding, verification, synthesis, lab validation, and production support, working with Ethernet, TCP/IP, and high-speed protocols.
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Responsibilities
Derive engineering specifications from system requirements and develop detailed architecture
Execute design using RTL and/or High-Level Synthesis (HLS, C++ to RTL) and ensure RTL quality via RDC, CDC, Formal, and Lint checks
Generate test plans and perform module-level verification, synthesis/STA, lab debug, and SW-driven validation on Linux-based SoC evaluation boards
Conduct silicon/FPGA bring-up, characterization, and support production ramp-up, including creation of collateral
Mentor and provide guidance on EDA tools (CDC, Lint, AC, RDC) and verification methodologies
Work hands-on with multiple complex designs from architecture to verification and synthesis
Qualification
Required
Bachelor's Degree in Electrical Engineering or equivalent (Masters + 2 years relevant experience acceptable)
Minimum 4 years of relevant experience developing, implementing, and verifying high-performance communications/networking ASIC/FPGA products
Active SECRET Clearance
Proficiency in VHDL design process and FPGA flow (Xilinx FPGA, Vivado)
Strong knowledge of Ethernet and TCP/IP protocols
Hands-on experience in logic/board debugging and analysis
Excellent written, verbal, and presentation skills
Preferred
Experience with High-Level Synthesis (Vivado HLS or Mentor Calypto)
Embedded software experience in C++ (OOP) and SystemVerilog Assertions (SVA)
Familiarity with high-speed protocols such as PCIe, Ethernet, and TCP/IP
Xilinx MPSoC design experience, including SDK/BSP development on bare metal or PetaLinux OS
Universal Verification Methodology (UVM) experience
Prior experience in Aerospace/Defense
Project leadership experience and knowledge of EVM