Google · 8 hours ago
Senior DFT Static Timing Analysis Engineer, Google Cloud
Sunnyvale, CA, USA
Full-time
Onsite
Senior Level
$156K/yr - $229K/yr
5+ years expGoogle is a leading technology company, and they are seeking a Senior DFT Static Timing Analysis Engineer for their Google Cloud division. In this role, you will shape the future of AI/ML hardware acceleration by driving cutting-edge TPU technology and developing custom silicon solutions for complex digital designs.
AppsArtificial Intelligence (AI)Cloud StorageSearch EngineSEO
Responsibilities
Own test mode timing constraint creation and validation, perform timing analysis and timing Engineering Change Order (ECO) creation, and oversee final timing sign-off for complex ASICs
Collaborate with the DFT team and optimize DFT architecture and also timing constraints to ensure successful timing closure
Participate in both static timing analysis methodology development and support, as well as chip implementation and timing signoff execution
Develop, support and execute implementation flows around industry-standard static timing and parasitic extraction tools
Debug flow issues reported by the team, and work with EDA vendors to resolve them where necessary
Qualification
Required
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience
5 years of experience in static timing (i.e., full chip timing signoff ownership, constraint authoring and verification, full chip static timing analysis and timing ECO creation, timing margins)
Experience in DFT architectures and associated test methodologies
Experience in Tessent generated DFT timing constraints, SSN bus networks and constraints and mode merging
Experience with EDA tools and EDA Tcl commands for timing analysis, timing closure, parasitic extraction, noise glitch, crosstalk
Experience with test mode timing constraint development
Preferred
Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture
10 years of experience in STA, and in leading test mode timing constraint development and timing convergence for SOC projects
Experience leading one or more aspects of physical design or physical design flow/methodology, to successful tape-outs and shipping silicon
Experience in extraction of design parameters, QoR metrics, and analyzing data trends
Experience in planning the clock distribution architecture for critical test modes
Knowledge of semiconductor device physics and SPICE simulation and full-chip static timing topics
Benefits
Bonus
Equity
Benefits
Company
Google specializes in internet-related services and products, including search, advertising, and software. It is a sub-organization of Alphabet.
10001+ employees
H1B Sponsorship
Google has a track record of offering H1B sponsorships. Please note that this does not
guarantee sponsorship for this specific role. Below presents additional info for your
reference. (Data Powered by US Department of Labor)
Distribution of Different Job Fields Receiving Sponsorship
Represents job field similar to this job
Trends of Total Sponsorships
2025 (8763)
2024 (8872)
2023 (9682)
2022 (11626)
2021 (9109)
2020 (9785)
Funding
Current Stage
Public CompanyTotal Funding
$26.1MKey Investors
Andy Bechtolsheim
2004-08-19IPO
1999-06-07Series Unknown· $25M
1998-11-01Angel· $1M
Leadership Team
Sundar Pichai
CEO
Thomas Kurian
CEO - Google Cloud
Recent News
Small Business Trends
2026-01-24
2026-01-24
Search Engine Journal
2026-01-24
Company data provided by crunchbase