Western Digital · 23 hours ago
Memory Chip Design Engineer
San Jose, CA
Full-time
Onsite
Senior Level, Lead/Staff
8+ years expWestern Digital is a company focused on powering global innovation and technology. They are seeking a Research Staff Member in the Design Group to develop and commercialize radiation hardened memory technology, working within a multi-functional team.
Big DataComputerHardwareManufacturingSoftware
Responsibilities
Developing high density memory chip custom layout
Including shared operational circuitry along with at pitch line drivers
All phases of chip design layout to be included: From architecture definition, density and performance optimization, final verification up to and including tape out
Running and Debugging Physical Verification flows including DRC, LVS, ERC and Antenna Checks
Minimize parasitic resistance and capacitance (R and C) in critical paths to meet timing and power consumption specifications
Comprehend and address reliability engineering issues such as electromigration, IR Drop and Design For Manufacturing robustness
Coordination of a Split-Fab Design and Development between WD (for Memory Array Layers) and a CMOS Foundry (for Operational Circuitry)
Developing and Harmonizing CMOS Foundry wafer requirements to allow for continued processing of Memory Array layers in WD’s Fabrication Line
Development of EDA Tool Design Rules for WD’s Memory Array Layers
Defining and executing the split-fab tape out flow
Qualification
Required
Minimum of a Bachelor's degree in Electrical Engineering, Physics, or closely related field with 8+ years of professional experience or a Ph.D. with 3+ years is required
Previous design layout, tape out and validation of high density memory chip designs
Capability to develop design layout schedules that meet chip functional requirements and timelines
Proficiency in Cadence Virtuoso (VXL), Mentor Graphics Calibre, or Synopsys IC Validator
Capability to work closely with circuit designers to iterate on schematics and with process engineers to understand fabrication constraints
Deep understanding of CMOS fabrication processes, Phase-Shift Mask Development and Multi-Patterning Techniques
Preferred
Experience developing memory cell models for inclusion in simulation tool environment, such as Verilog-A
Experience with emerging memories such as MRAM, ReRAM, or PCM
Experience developing Radiation Tolerant Layouts
Track record of publications and patents related to memory design layout
Benefits
Paid vacation time
Paid sick leave
Medical/dental/vision insurance
Life, accident and disability insurance
Tax-advantaged flexible spending and health savings accounts
Employee assistance program
Other voluntary benefit programs such as supplemental life and AD&D, legal plan, pet insurance, critical illness, accident and hospital indemnity
Tuition reimbursement
Transit
The Applause Program
Employee stock purchase plan
Western Digital Savings 401(k) Plan
Company
Western Digital
Western Digital helps customers capture, preserve, access, and transform an ever-increasing diversity of data.
10001+ employees
H1B Sponsorship
Western Digital has a track record of offering H1B sponsorships. Please note that this does not
guarantee sponsorship for this specific role. Below presents additional info for your
reference. (Data Powered by US Department of Labor)
Distribution of Different Job Fields Receiving Sponsorship
Represents job field similar to this job
Trends of Total Sponsorships
2025 (234)
2024 (537)
2023 (448)
2022 (580)
2021 (525)
2020 (332)
Funding
Current Stage
Public CompanyTotal Funding
$901.37M2023-10-31Post Ipo Debt· $1.37M
2023-01-31Post Ipo Equity· $900M
2015-09-30Post Ipo Equity
Leadership Team
Sesh Tirumala
SVP, CIO
A
Alvin B. Phillips
Founder
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