Intel Corporation · 9 hours ago
IP Logic Design Engineer
Austin, TX
Full-time
Hybrid
Senior Level
$122K/yr - $200K/yr
5+ years expIntel Corporation is a leader in engineering and technology, dedicated to creating world-changing technology. The IP Logic Design Engineer will be responsible for defining and designing microarchitecture for IP blocks, ensuring quality through verification and compliance, and supporting SoC customers for high-quality integration.
Semiconductors
Responsibilities
Defines, documents and designs the microarchitecture of IP blocks and subsystems
Owns the register transfer level (RTL) development for the IP block and implements the specification for logic components
Ensures quality of design through clean design partitioning, clear microarchitectural documentation, reviewing RTL design and verification of features
Applies various strategies, tools and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals
Delivers microarchitecture specifications (MAS) document along with detailed clear block diagram, signal level description, clocking details, power and timing requirements to capture the implementation details and ensure correct interactions between blocks or Ips
Reviews the verification plan and implementation to ensure design features are verified correctly and implements corrective measures for failing RTL tests to ensure correctness of features
Supports SoC customers to ensure high quality integration and verification of the IP block
Drives quality assurance compliance for smooth IP to SoC handoff
Supports post-silicon activity to enable various features
Good problem-solving ability
Excellent technical leadership/teamwork/communication skills and a proven ability to work with dynamic schedules
Qualification
Required
Candidate should possess a Bachelor's Degree – OR - Master's Degree in Electrical, Electronics or Computer Engineering
5+ years of experience in IP design for SoC or ASIC products
Experience in chip design with familiarity of the entire development flow from definition to tape-out
Experience in high-speed I/O protocols (e.g., PCIe, CXL, Ethernet, proprietary interconnects)
Experience with protocol conversion and coherency management between different domains (I/O and memory/coherent fabrics)
Ability to debug and resolve issues across multiple domains (I/O, coherency, ordering)
Proficiency in designing and verifying complex interface signals, including clock and power domain crossing
Hands-on experience with RTL design, simulation, debugging, triaging, running synthesis and timing analysis
Preferred
System simulation models and debugging RTL/tests
Experience in High-speed serial link protocols/IPs (PCIe, UPI, CXL, IOMMU etc)
Experience in Computer architecture and PCIe, UPI, CXL, IOMMU, Cache Coherency protocols
Experience in authoring Functional Specifications
Strong skills in interpreting and contributing to technical specifications and Solid problem-solving and analytical skills
Benefits
Competitive pay
Stock bonuses
Health
Retirement
Vacation
Company
Intel Corporation
Our mission is to shape the future of technology to help create a better future for the entire world, that’s the power of Intel Inside.
10001+ employees
H1B Sponsorship
Intel Corporation has a track record of offering H1B sponsorships. Please note that this does not
guarantee sponsorship for this specific role. Below presents additional info for your
reference. (Data Powered by US Department of Labor)
Distribution of Different Job Fields Receiving Sponsorship
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2025 (2793)
2024 (3717)
2023 (3576)
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2021 (3359)
2020 (1174)
Funding
Current Stage
Late StageLeadership Team
Brea Watts, MFA
Communications Manager, CEO
Carol Bartz
CEO
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