Amazon · 10 hours ago
Sr. Lead ASIC Design Engineer, Amazon Leo
Austin, TX
Full-time
Onsite
Senior Level, Lead/Staff
$159K/yr - $215K/yr
7+ years expAmazon is seeking a Sr. Lead ASIC Design Engineer for Amazon Leo, its low Earth orbit satellite network. The role involves defining and implementing digital chip SOCs for communications, optimizing design for performance and power, and collaborating with various teams to ensure high-quality silicon solutions.
Artificial Intelligence (AI)DeliveryE-CommerceFoundational AIRetail
No H1B
U.S. Citizen Only
Responsibilities
Implement system architecture in silicon from system specification to chip specification to RTL to optimizing timing/power to chip level validation
Develop solutions optimizing customer experience (throughput, latency, and availability) while meeting power and cost constraints
Drive high quality designs for first-time right silicon solutions, and meeting the power objectives through synthesis optimization and power analysis using industry-leading tools (RTLA, PTPX)
Perform static timing analysis (STA) and timing closure, ensuring designs meet timing constraints across all operating conditions
Develop and implement UPF (Unified Power Format) specifications for power intent and multi-voltage domain designs
Create standalone verification test bench to verify the correctness of your block
Work with the verification team and participate in System level verification using test benches constructed using UVM, System C and DPI-C
Ensure that the block meets DFT, timing and power targets by working closely with the implementation team
Engage with architects and system engineers to drive hardware micro-architecture
Lead design of 1 or more complex data path modules in System Verilog
Drive synthesis and physical implementation, working closely with backend teams to achieve timing closure and power targets
Perform power analysis using RTLA, PTPX, or other industry-leading tools to optimize power consumption
Develop and maintain UPF specifications for power management and multi-voltage domain designs
Conduct static timing analysis (STA) and resolve timing violations across multiple clock domains
Involve in control plane logic design and interfaces to bus fabrics
Explore and propose innovative ideas and work towards optimization of the design
Mentor and assign work to junior team members
Qualification
Required
Bachelor's degree in Electrical / Communications Engineering or related field, or equivalent experience
7+ years in FPGA digital logic design, preferably in DSP or communication systems
Preferred
Master's or Ph.D degree in Electrical / Communications Engineering
10+ years in FPGA digital design, preferably in communication systems
Benefits
Health insurance (medical, dental, vision, prescription, Basic Life & AD&D insurance and option for Supplemental life plans, EAP, Mental Health Support, Medical Advice Line, Flexible Spending Accounts, Adoption and Surrogacy Reimbursement coverage)
401(k) matching
Paid time off
Parental leave
Company
Amazon
Amazon is a tech firm with a focus on e-commerce, cloud computing, digital streaming, and artificial intelligence.
10001+ employees
Funding
Current Stage
Public CompanyTotal Funding
$8.11BKey Investors
AmazonKleiner Perkins
2023-01-03Post Ipo Debt· $8B
2001-07-24Post Ipo Equity· $100M
1997-05-15IPO
Leadership Team
Douglas J. Herrington
CEO, Worldwide Amazon Stores
Werner Vogels
VP & CTO
Recent News
2026-01-25
2026-01-25
2026-01-25
Company data provided by crunchbase