Google · 6 hours ago
RTL Design Engineer, Cloud TPU
Sunnyvale, CA, USA
Full-time
Onsite
Entry, Mid Level
$113K/yr - $161K/yr
2+ years expGoogle is seeking an RTL Design Engineer for Cloud TPU to shape the future of AI/ML hardware acceleration. In this role, you will develop custom silicon solutions and manage critical logic for next-generation data center accelerators, collaborating with various teams to ensure performance and security.
AppsArtificial Intelligence (AI)Cloud StorageSearch EngineSEO
Responsibilities
Translate high-level management requirements into detailed sub-block specifications and develop high-quality SystemVerilog for features like secure boot, reset controllers, and peripherals
Integrate industry-standard buses (e.g., APB, AHB, or AXI) to manage internal register maps and ensure seamless hardware-firmware synchronization
Partner with Design Verification (DV) teams to create comprehensive test plans and drive the resolution of functional issues in simulation and emulation
Collaborate with Physical Design teams to meet timing closure, area optimization, and manufacturability requirements for the control logic
Evaluate the impact of management features on the "always-on" power footprint and work with architects to enhance system efficiency
Qualification
Required
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related technical field, or equivalent practical experience
Experience in ASIC RTL design using systemverilog or verilog
Experience in scripting (e.g., Python, Tcl, or Perl) and debugging with tools like Verdi or VCS
Experience with soc bus protocols (e.g., APB, AHB, or AXI) and register-mapped architectures
Preferred
Master's degree or PhD in Electrical Engineering or Computer Engineering, with an emphasis on computer architecture
2 years of experience in ASIC design, specifically designing management and controllability subsystems or SoC chassis logic (e.g., Resets, Clocking, Fuse, or Security)
Experience with physical design teams to resolve congestion or timing issues in high-density control blocks
Experience in digital design fundamentals, including state machines, clock domain crossing (CDC), and reset synchronization, low-power design techniques
Familiarity with SoC bus protocols (e.g., APB, AHB, or AXI) and register-mapped architectures
Understanding of sideband protocols (e.g., I2C or SPI) and hardware-software interface (HSI) design
Benefits
Bonus
Equity
Benefits
Company
Google specializes in internet-related services and products, including search, advertising, and software. It is a sub-organization of Alphabet.
10001+ employees
H1B Sponsorship
Google has a track record of offering H1B sponsorships. Please note that this does not
guarantee sponsorship for this specific role. Below presents additional info for your
reference. (Data Powered by US Department of Labor)
Distribution of Different Job Fields Receiving Sponsorship
Represents job field similar to this job
Trends of Total Sponsorships
2025 (8763)
2024 (8872)
2023 (9682)
2022 (11626)
2021 (9109)
2020 (9785)
Funding
Current Stage
Public CompanyTotal Funding
$26.1MKey Investors
Andy Bechtolsheim
2004-08-19IPO
1999-06-07Series Unknown· $25M
1998-11-01Angel· $1M
Leadership Team
Sundar Pichai
CEO
Thomas Kurian
CEO - Google Cloud
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