Google · 10 hours ago
SoC RTL Design Engineer, TPU
Sunnyvale, CA, USA
Full-time
Onsite
Entry, Mid Level
$132K/yr - $189K/yr
2+ years expGoogle is seeking a SoC RTL Design Engineer to shape the future of AI/ML hardware acceleration. In this role, you will drive cutting-edge TPU technology, focusing on designing complex clocking infrastructures for next-generation accelerators.
AppsArtificial Intelligence (AI)Cloud StorageSearch EngineSEO
Responsibilities
Define specifications and develop SystemVerilog for advanced clocking features, including FLL/PLL controllers, dividers, and glitch-free multiplexer logic
Design and optimize dynamic power-saving mechanisms such as clock skipping (pulse swallowing), frequency scaling sequences, and fine-grained clock gating
Partner with architecture teams to evaluate clock-tree impacts and implement infrastructure supporting various SoC power states and performance levels
Collaborate with Physical Design teams to manage skew, jitter, and multi-cycle paths, ensuring the CCU meets stringent timing and area goals
Work with Design Verification and Silicon bring-up teams to create test plans for clocking corner cases and root-cause issues in simulation and emulation
Qualification
Required
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience
2 years of experience in ASIC RTL design, with a focus on clocking, reset, or timing-critical RTL development
Experience with digital clock control circuits, including clock dividers, glitch-free muxes, and clock gating
Experience in SystemVerilog for creating microarchitecture specifications and synthesizable RTL
Experience with design quality tools, specifically for Clock Domain Crossing (CDC), linting, and static timing analysis
Experience using Python, Tcl, or Perl for automating design tasks and data analysis
Preferred
Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture
5 years of experience with high-performance ASIC design in PLL, FLL, and DLL integration
Experience implementing clock skipping, Dynamic Voltage and Frequency Scaling (DVFS), and fine-grained clock gating for low-power SoC optimization
Proficiency in Python or Perl for automating design scripts and analyzing complex clock-tree data
Understanding of clock distribution challenges, including jitter, skew management, and duty-cycle distortion
Ability to lead cross-functional efforts from initial specification through silicon bring-up
Benefits
Bonus
Equity
Benefits
Company
Google specializes in internet-related services and products, including search, advertising, and software. It is a sub-organization of Alphabet.
10001+ employees
H1B Sponsorship
Google has a track record of offering H1B sponsorships. Please note that this does not
guarantee sponsorship for this specific role. Below presents additional info for your
reference. (Data Powered by US Department of Labor)
Distribution of Different Job Fields Receiving Sponsorship
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2025 (8763)
2024 (8872)
2023 (9682)
2022 (11626)
2021 (9109)
2020 (9785)
Funding
Current Stage
Public CompanyTotal Funding
$26.1MKey Investors
Andy Bechtolsheim
2004-08-19IPO
1999-06-07Series Unknown· $25M
1998-11-01Angel· $1M
Leadership Team
Sundar Pichai
CEO
Thomas Kurian
CEO - Google Cloud
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