AMD · 15 hours ago
Tile-Level Place & Route (PnR) - Physical Design Engineer
Austin, TX
Full-time
Hybrid
Mid, Senior Level
$171K/yr - $257K/yrAMD is a company focused on building innovative products that enhance computing experiences across various domains including AI and data centers. They are seeking a Physical Design Engineer who will be responsible for the implementation and optimization of physical design for high-performance IP blocks and tiles within complex SoCs, with a strong emphasis on timing closure and power-performance-area optimization.
AI InfrastructureArtificial Intelligence (AI)Cloud ComputingComputerEmbedded SystemsGPUHardwareSemiconductor
No H1B
Responsibilities
Perform floorplanning, power grid design, placement, clock tree synthesis (CTS), routing, and chip finishing for tile-level designs
Execute PnR flows from netlist to GDSII using industry-standard EDA tools (Cadence Innovus, Synopsys ICC2/FC)
Drive timing closure at block and tile level using STA tools (PrimeTime)
Conduct IR-drop/EM analysis and signal integrity checks
Optimize designs for power, performance, and area (PPA)
Implement advanced low-power strategies such as multi-Vt optimization, power gating, clock gating, dynamic voltage/frequency scaling (DVFS), and retention flops
Ensure compliance with power intent specifications (UPF/CPF)
Perform physical verification (DRC/LVS) using tools like Calibre
Ensure compliance with design rules and manufacturing constraints
Work closely with RTL, architecture, and SoC integration teams to meet design specifications
Coordinate with FCFP/FCT team for tile closure
Develop and maintain scripts (Tcl, Perl, Python) to automate design flows and improve efficiency
Contribute to methodology improvements for advanced nodes (3nm and below)
Implement ECOs for timing and functional fixes at tile level
Qualification
Required
Bachelor's or Master's degree in Computer Engineering, Electrical Engineering, or a related field
Preferred
Physical design with strong hands-on PnR experience
Advanced technology nodes (7nm, 5nm, or below)
Tools: Cadence Innovus, Synopsys FC, PrimeTime, Calibre, Redhawk
Strong scripting skills (Tcl, Perl, Python)
CPU/GPU/DPU or high-performance IP design experience
Understanding of computer architecture and SoC design flows
Excellent problem-solving, communication, and ability to work with geographically distributed teams
Familiarity with chip-level integration and tile partitioning strategies
Proven track record of closing large designs (>2M instances, >2.5GHz frequency)
Benefits
AMD benefits at a glance.
Company
AMD
Advanced Micro Devices is a semiconductor company that designs and develops graphics units, processors, and media solutions.
Founded in 1969
10001+ employees
Funding
Current Stage
Public CompanyTotal Funding
unknownKey Investors
OpenAIDaniel Loeb
2025-10-06Post Ipo Equity
2023-03-02Post Ipo Equity
2021-06-29Post Ipo Equity
Leadership Team
Lisa Su
Chair & CEO
Mark Papermaster
CTO and EVP
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