SEAKR · 14 hours ago
Senior FPGA Engineer
6221 S Racine Cir, Englewood, CO 80111, USA
Full-time
Onsite
Senior Level, Lead/Staff
$130K/yr - $185K/yr
10+ years expSEAKR Engineering is a leading-edge provider of advanced electronics for space applications. They are seeking a Senior FPGA Engineer with extensive knowledge in digital circuit design and FPGA development to lead small teams and complete complex designs.
AerospaceData ManagementHardwareManufacturingMechanical EngineeringSecuritySoftware Engineering
No H1B
U.S. Citizen Only
Responsibilities
Completing multiple FPGA or ASIC design using Verilog and/or VHDL, including at least one of moderate complexity
Demonstrate knowledge and development of a test bench with self-checking and simulation (including back annotated timing) for given FPGA modules, top level FPGA, and system with multiple FPGAs
FPGA technology differences (Xilinx vs Actel/Microsemi)
FPGA process and development flows, especially flows using Synplify Pro, ISE, Vivado and Libero
Scripting languages such as TCL or Python
Leading small sized teams in order to develop moderately complex systems according to program schedule expectations
FPGA design experience including thorough design documentation, completion and review of RTL blocks, participation in code reviews, significant RTL debug, and working knowledge of CDC, reset and clock design
Ability to solve digital lab debug problems with use of lab tools such as bench supplies, scopes and logic analyzers
Qualification
Required
Extensive knowledge of digital circuit design, state machines, Boolean math and FPGAs
Experience with completing multiple FPGA or ASIC design using Verilog and/or VHDL, including at least one of moderate complexity
Demonstrate knowledge and development of a test bench with self-checking and simulation (including back annotated timing) for given FPGA modules, top level FPGA, and system with multiple FPGAs
FPGA technology differences (Xilinx vs Actel/Microsemi)
FPGA process and development flows, especially flows using Synplify Pro, ISE, Vivado and Libero
Scripting languages such as TCL or Python
Leading small sized teams in order to develop moderately complex systems according to program schedule expectations
FPGA design experience including thorough design documentation, completion and review of RTL blocks, participation in code reviews, significant RTL debug, and working knowledge of CDC, reset and clock design
Ability to solve digital lab debug problems with use of lab tools such as bench supplies, scopes and logic analyzers
Candidate shall also have leadership skills and ability to provide support and technical direction to junior engineers
Clear written and verbal communication skills are required
Must have at least 10+ years of FPGA experience
US Citizenship Required
Preferred
Knowledge of RTL design techniques for radiation upset mitigation
Experience using multiple RTL languages
A Bachelor's degree in Electrical Engineering or Computer Science is desired
Benefits
Rich medical, dental and vision insurance plans
Generous 401(k) retirement plan
Year-end bonus
Paid leave, such as vacation, sick, bereavement, and FMLA
Company
SEAKR
SEAKR, a wholly owned subsidiary of RTX, is a Leading-Edge Provider of Advanced Space Electronics Solutions.
201-500 employees
Funding
Current Stage
Growth StageTotal Funding
unknown2021-09-14Acquired
Leadership Team
David Anderson
Vice President, Product Development and Chief Technology Officer
Chad Fisher, Ph.D.
Chief Operating Officer
Recent News
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2025-02-10
Google Patent
2024-04-14
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