Eridu · 16 hours ago
ASIC Chip Design Lead
San Francisco Bay Area
Full-time
Onsite
Senior Level, Lead/Staff
$250K/yr - $280K/yr
3+ years expEridu is a Silicon Valley-based hardware startup focusing on infrastructure solutions for large-scale AI models. They are looking for a hands-on ASIC Chip Design Lead to oversee chip design execution from micro-architecture through full-chip integration and timing signoff, while also providing leadership across design, verification, and physical design teams.
AI InfrastructureArtificial Intelligence (AI)Machine LearningSemiconductor
Responsibilities
Write, review, and debug production-quality RTL in Verilog/SystemVerilog
Own RTL blocks end-to-end from specification through signoff
Make timing-, area-, and power-aware design decisions at the RTL and micro-architecture levels
Perform detailed code reviews and set a high technical bar for RTL quality
Draft detailed micro-architecture specifications derived from architecture documents and feature requirements
Translate high-level requirements into implementable pipelines, control logic, datapaths, and corner-case handling
Clearly define performance, latency, and resource tradeoffs to unblock RTL and verification execution
Work closely with Physical Design to improve synthesis and place-and-route timing
Iterate on RTL, hierarchy, micro-architecture, and floorplanning to address timing, congestion, and QoR issues
Analyze synthesis and P&R reports and proactively drive timing, area, and power improvements
Partner with Design Verification to debug functional and performance issues
Review functional and code coverage and provide actionable feedback
Own bugs from discovery through fix, validation, and closure
Own full-chip RTL integration and block roll-up
Run chip-level synthesis, define constraints, and close chip-level timing
Deliver timing-clean netlists to Physical Design that meet performance targets
Drive block- and chip-level design checklists as execution quality gates
Review checklist status with designers and proactively push closure of open items
Continuously refine design methodologies, checklists, and flows based on silicon learnings
Lead by technical authority and hands-on execution rather than coordination alone
Qualification
Required
Strong hands-on experience with RTL design and micro-architecture
Proven experience with full-chip integration and timing closure
Led at least one full-chip tape-out within the last 3 years, with direct responsibility for design signoff and PD handoff
Deep understanding of synthesis, static timing analysis, and physical-design collaboration
Experience refactoring and restructuring RTL to resolve timing, area, and congestion challenges
Comfortable working cross-functionally with architecture, verification, firmware, and physical design teams
Demonstrated ability to drive execution in ambiguous, fast-moving environments
Preferred
Silicon bring-up experience, including post-silicon debug and RTL-to-silicon correlation
Hands-on experience defining and refining SDC constraints and improving post-layout timing
Knowledge of high-performance networking architectures and Ethernet-based systems
Familiarity with Ultra Ethernet and/or UCIe chip-to-chip interconnect protocols
Experience with chiplet-based system design
Company
Eridu
Eridu is a Silicon Valley startup focused on accelerating the performance of large AI models.
51-200 employees
H1B Sponsorship
Eridu has a track record of offering H1B sponsorships. Please note that this does not
guarantee sponsorship for this specific role. Below presents additional info for your
reference. (Data Powered by US Department of Labor)
Distribution of Different Job Fields Receiving Sponsorship
Represents job field similar to this job
Trends of Total Sponsorships
2025 (3)
Funding
Current Stage
Growth StageLeadership Team
Drew Perkins
Chief Executive Officer
Omar Hassen
Co-founder and Chief Product Officer
Company data provided by crunchbase