TPU RTL Design Engineer, Networking and Inter-Chip-Interconnects jobs in United States
cer-icon
Apply on Employer Site
company-logo

Google · 11 hours ago

TPU RTL Design Engineer, Networking and Inter-Chip-Interconnects

positionSunnyvale, CA
timeFull-time
remoteOnsite
seniorityMid Level
money$113K/yr - $161K/yr

Google is a leading technology company focused on AI and machine learning innovations. In this role, you will work on designing RTL IP for TPU technology, contributing to the development of custom silicon solutions that power Google's AI applications and infrastructure.

AppsArtificial Intelligence (AI)Cloud StorageSearch EngineSEO
check
Growth Opportunities
check
H1B Sponsor Likelynote

Responsibilities

Work independently and collaboratively to create and review ASIC/SoC subsystem design architecture and microarchitecture specifications for different elements in the network stack
Develop SystemVerilog RTL to implement logic for ASIC/SoC products according to established coding and quality guidelines
Own the complete RTL lifecycle from initial coding and documentation to ensuring sign-off readiness for Lint, CDC, and synthesis
Work with Design Validation (DV) teams to create testplans for, verify, and debug design RTL. Work with architecture and power teams to evaluate features and their impact
Work with physical design teams to ensure design meets physical requirements and timing closure

Qualification

ASIC RTL designSystemVerilogEDA toolsDigital design fundamentalsScripting languagesAI code-generationDebugging toolsCross-functional collaboration

Required

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience
Experience in ASIC RTL design using SystemVerilog or Verilog
Experience with industry-standard EDA tools for simulation, synthesis and power analysis

Preferred

Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture
Experience working cross-functionally with DV and PD teams
Experience with CDC, RDC, RTL Linting and LEC
Strong understanding of digital design fundamentals, including synchronous and asynchronous logic, state machines, and bus protocols
Ability to leverage scripting languages or AI code-generation to accelerate the RTL design process
Basic proficiency in scripting (Python, Tcl, or Perl) and debugging with tools like Verdi or VCS

Benefits

Bonus
Equity
Benefits

Company

Google

twittertwittertwitter
Glassdoor4.4
company-logo
Google specializes in internet-related services and products, including search, advertising, and software. It is a sub-organization of Alphabet.
dateFounded in 1998
location
Mountain View, California, USA
people-size10001+ employees
web-link
https://www.google.com

H1B Sponsorship

Google has a track record of offering H1B sponsorships. Please note that this does not guarantee sponsorship for this specific role. Below presents additional info for your reference. (Data Powered by US Department of Labor)
Distribution of Different Job Fields Receiving Sponsorship
Represents job field similar to this job
Trends of Total Sponsorships
2025 (8763)
2024 (8872)
2023 (9682)
2022 (11626)
2021 (9109)
2020 (9785)

Funding

Current Stage
Public Company
Total Funding
$26.1M
Key Investors
Andy Bechtolsheim
2004-08-19IPO
1999-06-07Series Unknown· $25M
1998-11-01Angel· $1M

Leadership Team

leader-logo
Sundar Pichai
CEO
linkedin
leader-logo
Thomas Kurian
CEO - Google Cloud
linkedin

Recent News

Small Business Trends
Google Gemini Enhances API with Direct Data Inputs and Larger File Support
2026-01-24
Android Authority
A major Pixel-exclusive security feature could be the Galaxy S26’s secret weapon
2026-01-24
Search Engine Journal
User Data Is Important In Google Search, Per Liz Reid’s DOJ Filing via @sejournal, @marie_haynes
2026-01-24
Company data provided by crunchbase