d-Matrix · 5 hours ago
Principal ATE Test Engineer
Santa Clara, CA
Full-time
Hybrid
Lead/Staff
12+ years expd-Matrix is focused on unleashing the potential of generative AI to power the transformation of technology. They are seeking a Principal ATE Test Engineer to lead ATE test solutions for complex silicon SoC products, overseeing test strategies and interacting with manufacturing partners.
AI InfrastructureArtificial Intelligence (AI)Cloud InfrastructureData CenterSemiconductor
Responsibilities
Develop and oversee SoC test strategy
Interact with manufacturing partners
Define and implement ATE programs
Own the product from design and initial samples all the way through high volume production ramp
Identify and drive test cost reduction
Improve both CP and FT yield
Identify FT high yield fallout bins
Enhance CP program to minimize high FT yield fallout bins
Qualification
Required
Strong academic and technical background in electrical engineering. At minimum, a bachelor's in EE is required, and a master's is preferred
12 + years of experience developing & releasing complex SoC/silicon products to high volume manufacturing
Experience with developing high pin count wafer sort probe cards and load boards
Has implemented Scan, at speed Scan, MBist, Serdes loopback
Working knowledge of high-speed protocols like PCIe, LPDDRx, HBM, etc
Professional attitude with the ability to execute multiple tasks with minimal supervision
Strong team player with good communication skills to work alongside a team of high caliber engineers
Entrepreneurial, open-mind behavior and can-do attitude
Hands-on experience with high-speed SoC test program/hardware development on the Advantest 93k test platform
Collaboration with the design DFT team to define test strategy and create and own the test plan
Familiar with high-speed and high power load board design techniques
Proven track record of implementing ATE patterns to optimize tester resources and minimize ATE test time while maintaining product quality
Strong knowledge and development of DFT techniques implemented in silicon that provide maximum defect and parametric device coverage—AC/DC SCAN, MBIST, DBIst, DSerDes, DDR, D2D, DIMC, and other functional tests
Strong knowledge of lot genealogy from 2DiD barcode down to ECID in eFuse for device serial number, chiplet ID, and die information
Expertise in production testing of high speed SerDes operating at 16 Gbps and higher
Skilled in ATE programming, silicon/ATE bring-up, bench-ATE correlation, and debug
Experience with lab equipment, including protocol analyzers and oscilloscopes
Experience with data conversion between STDF file format into csv file format using scripts, including extracting ECID reside with eFuse block
Proficiency in modern programming languages such as C/C++ and Python
Preferred
Fluent in data processing using high level programming languages
Experience in running internal loopback at wafer sort as well as at FT
Familiarity with database setup using JMP as YMS (Yield Management Tool)
Company
d-Matrix
D-Matrix is a platform that enables data centers to handle large-scale generative AI inference with high throughput and low latency.
51-200 employees
H1B Sponsorship
d-Matrix has a track record of offering H1B sponsorships. Please note that this does not
guarantee sponsorship for this specific role. Below presents additional info for your
reference. (Data Powered by US Department of Labor)
Distribution of Different Job Fields Receiving Sponsorship
Represents job field similar to this job
Trends of Total Sponsorships
2025 (20)
2024 (15)
2023 (8)
2022 (7)
Funding
Current Stage
Growth StageTotal Funding
$429MKey Investors
Temasek HoldingsTSVC
2025-11-12Series C· $275M
2023-09-06Series B· $110M
2022-04-20Series A· $44M
Leadership Team
Peter Buckingham
Senior Vice President, Software Engineering
Recent News
2026-01-24
2026-01-22
2025-12-22
Company data provided by crunchbase