Intel Corporation · 23 hours ago
Senior Physical Design Application Engineer
US, Arizona, Phoenix
Full-time
Hybrid
Mid, Senior Level
$122K/yr - $232K/yr
4+ years expIntel Corporation is a leader in the semiconductor industry, and they are seeking a Senior Physical Design Application Engineer to provide technical support to Intel Foundry Services customers. This role involves driving quality improvements in design kits and supporting customers through successful tape-outs with a focus on advanced CMOS processes.
Semiconductors
No H1B
Security Clearance RequiredU.S. Citizen Only
Responsibilities
Provide comprehensive technical support to Intel Foundry Services customers on PDKs, digital reference flows, and digital design signoff methodologies
Support and deliver ASIC/Digital tool/flow/methodology solutions using Cadence tool suites to address customer issues and ensure successful tape-outs
Drive customer success through expert guidance on advanced CMOS process implementation
Drive quality improvements in design kits and documentation through ASIC design reference flow validation and comprehensive documentation review
Create application notes, technical content, and deliver training presentations to customers and internal teams
Establish and maintain quality assurance processes for design flow validation
Develop and optimize digital design implementation flows for advanced CMOS processes
Support hierarchical and multi-voltage domain design approaches, timing and physical convergence
Build and maintain quality assurance (QA) regression frameworks for design validation
Qualification
Required
US Citizenship required
Ability to obtain a US Government Security Clearance
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or STEM-related field of study
4+ years of experience with advanced CMOS processes (22nm and below)
3+ years of experience in ASIC physical design implementation and/or ASIC design signoff (SoC/ASIC)
3+ years of experience in one of the following scripting languages (i.e. Python, Perl, Tcl, shell scripting)
Preferred
Active US Government Security Clearance with a minimum of Secret level
Post Graduate degree in Electrical / Computer Engineering, Computer Science, or in a STEM related field of study
Customer-facing experience in technical support roles
Experience with state-of-the-art process technology (7nm and below)
Hands-on experience in Cadence EDA-based ASIC design implementation including full-chip integration, synthesis, APR, static timing analysis, layout verification, and reliability verification
Proficiency with Cadence EDA tools and flows: Innovus, Tempus, TempusECO, Pegasus, Voltus
Experience with Synopsys tools (Fusion Compiler, PrimeTime, Prime ECO, ICV) is a plus
Experience with hierarchical and multi-voltage domain design, top-down design, budgeting, and correlation across implementation and verification tools
Benefits
Competitive pay
Stock bonuses
Health
Retirement
Vacation
Company
Intel Corporation
Our mission is to shape the future of technology to help create a better future for the entire world, that’s the power of Intel Inside.
10001+ employees
Funding
Current Stage
Late StageLeadership Team
Brea Watts, MFA
Communications Manager, CEO
Carol Bartz
CEO
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