Scalence L.L.C. · 4 weeks ago
Silicon Design Verification Engineer (III)
Santa Barbara, CA
Full-time
Onsite
Mid Level
$96.81/hr - $112.44/hrScalence L.L.C. is seeking a Silicon Design Verification Engineer (III) to contribute to a medium-sized project of moderate impact. The role involves driving outcomes through verification execution and collaboration with teams to ensure the functional correctness of logic design.
Information Technology & Services
Responsibilities
Developing test plans, including verification strategy, environment, components, stimulus, checks, and coverage, ensuring documentation is clear and accessible
Collaborating closely with architecture and design teams to verify the functional correctness of logic design
Working with cross-functional teams to debug failures, such as boards, software, manufacturing, design, and thermal issues, and providing quality solutions
Applying verification techniques and methodologies to drive design verification
Utilizing verification tools and languages, such as SystemVerilog, to drive design verification
Qualification
Required
SV Coding Skills
Simulation-based Verification Techniques, Methodology, and Experience
Scripting and infrastructure
Domain-specific knowledge
Testbench components and techniques
UVM Coding Skills
SVA Coding Skills
Python Scripting
Formal Verification Techniques, Methodology, and Experience
Communication and comprehension
Problem-solving
Company
Scalence L.L.C.
In today’s dynamic and competitive market, success hinges on mastering three key areas: Data Intelligence, Business Resilience, and Digital Experience.
501-1000 employees
Funding
Current Stage
Late StageCompany data provided by crunchbase