Infineon Technologies · 19 hours ago
Principal Engineer ASIC/Layout Design
Andover, MA
Full-time
Onsite
Senior Level, Lead/Staff
$132K/yr - $181K/yr
10+ years expInfineon Technologies is a global leader in semiconductor solutions in power systems and IoT, enabling game-changing solutions for green and efficient energy. As a Principal Engineer ASIC-Layout Design, you will be responsible for leading layout engineering efforts, implementing physical layouts, and collaborating with design engineers to drive product development and innovation.
Consumer ElectronicsElectronicsEnergy EfficiencyManufacturingSemiconductor
Responsibilities
Principal Layout engineer responsible for Layout of top and block level schematics
Responsible as Lead Layout support product development and TO activities
Implement Physical layout at block and top levels utilizing best practices for matching, shielding, dummies, fills, and isolation
Work with design engineers on sizing and matching trade off on the block level
Provide floor planning strategy for different power management IC’s
Create tape out documentation including LVS, ERC and DRC checks on block and top level
Work with technology and pdk engineers to understand and if possible eliminates all non relevant DRC errors
Qualification
Required
Experience with Tape out procedures
Associate or Bachelors in EE or other equivalent studies with 10+ years of relevant experience, preferred in Analog layout
Guide and train junior engineers
Experience with Cadence Virtuoso, Assura, and Calibre with an understanding of PDK's, PCELL's, layers, etc
The successful candidate will need to be a very organized and detail oriented individual
The candidate will be required to communicate well and work well with team members
The candidate must also be highly motivated, innovative, and capable of driving tasks to a successful conclusion
Thorough knowledge of industry standard EDA tools from Cadence
Must be able to set up LVS, DRC, ERC environments and debug verification issues using Cadence tools
Experience with layout of high power power management IC's
Experience with floor planning, die size estimates, block level routing and top level chip assembly
Knowledge of high performance analog layout techniques such as common centroid layout, shielding, use of dummy devices, thermal aware layout with consideration for electromigration
Demonstrated experience with analog layout for silicon chips in mass production
Experience working with remote design teams
Reading and interpreting Design Rule Manuals
Benefits
All employees will be eligible to participate in an incentive plan
Company
Infineon Technologies
Infineon Technologies offers semiconductor solutions, microcontrollers, LED drivers, sensors and Automotive & Power Management ICs.
10001+ employees
H1B Sponsorship
Infineon Technologies has a track record of offering H1B sponsorships. Please note that this does not
guarantee sponsorship for this specific role. Below presents additional info for your
reference. (Data Powered by US Department of Labor)
Distribution of Different Job Fields Receiving Sponsorship
Represents job field similar to this job
Trends of Total Sponsorships
2025 (2)
2024 (8)
2023 (12)
2022 (4)
2021 (11)
2020 (4)
Funding
Current Stage
Public CompanyTotal Funding
$5.55BKey Investors
European Commission
2025-02-20Grant· $966.23M
2025-02-07Post Ipo Debt· $774.86M
2025-02-04Post Ipo Debt· $2.07B
Leadership Team
Sven Schneider
Chief Financial Officer and Member of the Executive Board
Laurent Rémont
SVP & GM MEMS and Magnetics
Recent News
2026-02-04
2026-02-04
Company data provided by crunchbase