Qualcomm · 1 hour ago
Senior Design Verification Engineer
Qualcomm Atheros, Inc. is a leading technology company specializing in wireless communication and connectivity solutions. The Senior Design Verification Engineer will contribute to ASIC verification efforts for IPs, subsystems, and SoCs, collaborating with various teams to ensure the delivery of high-quality products.
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Responsibilities
Verify IPs, subsystems, and SoCs used across Qualcomm Wi‑Fi, connectivity, and IoT platforms
Explore and apply innovative design verification methodologies, including simulation, formal verification, and emulation, to continuously improve testbench quality and efficiency
Own end‑to‑end low‑power verification, including testbench architecture, test plan development, and coverage‑driven verification closure
Collaborate with cross‑geography teams on IP, SoC, and verification infrastructure deliveries, including milestone planning and critical debug activities
Serve as a technical point of contact for IP and SoC design teams, providing verification guidance and support
Work closely with cross‑functional stakeholders to ensure the delivery of high‑quality, robust IPs to SoC product teams
Qualification
Required
3+ years of practical ASIC design verification experience, including ownership of verification for complex SoC subsystems or IP blocks
Strong experience across digital design verification, including test automation, constrained‑random testing, code and functional coverage, SystemVerilog assertions (SVA), and performance verification
Proven expertise in SystemVerilog and UVM‑based verification methodologies, including assertion‑based and coverage‑driven verification
Strong analytical, debugging, and problem‑solving skills, with the ability to lead complex technical investigations
Experience with C/C++ and assembly language, particularly for test development, modeling, or debug
Solid understanding of AMBA bus protocols (e.g., AXI, AHB, APB)
Knowledge of low‑power design concepts and power management techniques is a strong plus
Experience with gate‑level simulation (GLS) and timing‑aware verification is a plus
Proficiency in scripting languages such as Python and/or Perl for automation and productivity
Strong communication skills and the ability to work effectively as part of a global, cross‑functional team
Demonstrated leadership skills, with the ability to mentor junior engineers and drive verification best practices
Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience
OR Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience
OR PhD in Science, Engineering, or related field
Preferred
Knowledge of low‑power design concepts and power management techniques is a strong plus
Experience with gate‑level simulation (GLS) and timing‑aware verification is a plus
Benefits
Competitive annual discretionary bonus program
Opportunity for annual RSU grants
Highly competitive benefits package
Company
Qualcomm
Qualcomm designs wireless technologies and semiconductors that power connectivity, communication, and smart devices.
H1B Sponsorship
Qualcomm has a track record of offering H1B sponsorships. Please note that this does not
guarantee sponsorship for this specific role. Below presents additional info for your
reference. (Data Powered by US Department of Labor)
Distribution of Different Job Fields Receiving Sponsorship
Represents job field similar to this job
Trends of Total Sponsorships
2025 (2013)
2024 (1910)
2023 (3216)
2022 (2885)
2021 (2104)
2020 (1181)
Funding
Current Stage
Public CompanyTotal Funding
$3.5M1991-12-20IPO
1988-01-01Undisclosed· $3.5M
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