Capgemini Engineering · 17 hours ago
Senior Analog Layout Engineer
San Francisco, CA
Full-time
Onsite
Senior Level, Lead/Staff
$98K/yr - $183K/yr
10+ years expCapgemini Engineering is a world leader in engineering services, bringing together a global team to help innovative companies. The Senior Analog Layout Engineer will be responsible for the layout of high-performance analog cores and leading IC layout of cutting-edge CMOS integrated circuits.
ConsultingInformation ServicesInformation TechnologyInnovation ManagementMechanical Engineering
Responsibilities
Thorough knowledge of industry‑standard EDA tools from Cadence, Mentor, and Synopsys
Ability to set up LVS, DRC, and ERC environments and debug verification issues using Cadence and Mentor tools
Experience with layout of high‑performance analog blocks such as analog‑to‑digital converters, references, digital‑to‑analog converters, PLLs, etc
Experience with floor planning, block‑level routing, and top‑level chip assembly
Knowledge of high‑performance analog layout techniques, including common‑centroid layout, shielding, use of dummy devices, and thermal‑aware layout with consideration for electromigration
Demonstrated experience with analog layout for silicon chips in mass production
Experience working with distributed design teams
Knowledge of SKILL code and layout automation
Self‑starter with the ability to define and adhere to a schedule
Strong written and verbal communication skills
Qualification
Required
Thorough knowledge of industry‑standard EDA tools from Cadence, Mentor, and Synopsys
Ability to set up LVS, DRC, and ERC environments and debug verification issues using Cadence and Mentor tools
Experience with layout of high‑performance analog blocks such as analog‑to‑digital converters, references, digital‑to‑analog converters, PLLs, etc
Experience with floor planning, block‑level routing, and top‑level chip assembly
Knowledge of high‑performance analog layout techniques, including common‑centroid layout, shielding, use of dummy devices, and thermal‑aware layout with consideration for electromigration
Demonstrated experience with analog layout for silicon chips in mass production
Experience working with distributed design teams
Knowledge of SKILL code and layout automation
Self‑starter with the ability to define and adhere to a schedule
Strong written and verbal communication skills
10+ years of experience in high‑performance analog layout in advanced CMOS process
Preferred
Experience With FinFET Process Nodes
Benefits
Paid time off based on employee grade (A-F), defined by policy: Vacation: 12-25 days, depending on grade, Company paid holidays, Personal Days, Sick Leave
Medical, dental, and vision coverage (or provincial healthcare coordination in Canada)
Retirement savings plans (e.g., 401(k) in the U.S., RRSP in Canada)
Life and disability insurance
Employee assistance programs
Other benefits as provided by local policy and eligibility
Company
Capgemini Engineering
Capgemini Engineering is a global innovation and engineering consulting firm.
Founded in 1982Paris, Ile-de-France, FRA
10001+ employees
H1B Sponsorship
Capgemini Engineering has a track record of offering H1B sponsorships. Please note that this does not
guarantee sponsorship for this specific role. Below presents additional info for your
reference. (Data Powered by US Department of Labor)
Distribution of Different Job Fields Receiving Sponsorship
Represents job field similar to this job
Trends of Total Sponsorships
2022 (1)
2021 (12)
2020 (24)
Funding
Current Stage
Public CompanyTotal Funding
$4M2019-06-24Acquired
2006-09-19Post Ipo Equity· $4M
1990-01-05IPO
Leadership Team
Joao Neiva
Automotive Mobility Experience Offer Leader
Pascal Brier
Group EVP Strategy, Technology & Inovation
Recent News
2025-11-23
Mexico Business
2025-11-19
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