Indotronix Avani Group · 10 hours ago
Electrical Engineer
Indotronix Avani Group is seeking a Sr Electrical Engineer to join their FPGA & ASIC Design Solutions team. This role involves capturing requirements, designing digital architectures, and verifying systems for military GPS products.
Responsibilities
Requirements capture, ASIC / FPGA digital architecture and design using RTL, timing analysis and closure, verification, and system integration
RTL coding and simulation in VHDL or Verilog
Testbench development for the verification of RTL blocks using VHDL or SystemVerilog
Qualification
Required
Need Active Secret Clearance
Requirements capture, ASIC / FPGA digital architecture and design using RTL, timing analysis and closure, verification, and system integration
RTL coding and simulation in VHDL or Verilog
Testbench development for the verification of RTL blocks using VHDL or SystemVerilog
RTL coding and simulation in VHDL or Verilog OR Testbench development for the verification of RTL blocks using UVM and SystemVerilog
Digital circuit architecture, design, resource tradeoffs, timing analysis and timing closure
Proficiency using ASIC and/or FPGA simulation and synthesis tools (e.g. Modelsim, Synopsys, FPGA-specific tools)
Familiarity with revision control concepts and tools (e.g. Subversion)
Ability to work with minimal supervision, part of a team of engineers with a variety of skills and backgrounds
Strong oral and written communication skills and the ability to document and present one's work and status
Bachelor's Degree in applicable engineering field
Preferred
Familiarity with best practice chip-level verification techniques and languages (e.g. constrained random, functional coverage, SystemVerilog)
ASIC / FPGA lab validation with advanced lab equipment
Design for Test (DFT) and manufacturability issues
Experience with Unix, scripting, C/C++, and/or Perl
Company
Indotronix Avani Group
Indotronix Avani Group is a consultancy that offers machine learning, cloud computing, software development and SaaS services.
Funding
Current Stage
Late StageRecent News
2023-12-25
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