Scalence L.L.C. · 16 hours ago
Silicon Validation Engineer 4
Scalence L.L.C. is a dynamic team responsible for building engineering systems and automation, particularly around FPGA tool data extraction. The role involves contributing to automation and data analytics efforts to enhance the efficiency and effectiveness of engineering processes.
Information Technology & Services
Responsibilities
Develop scripts to extract metrics from Vivado implementation runs
Automate the collection of timing, utilization, and quality metrics using TCL and Python
Integrate extracted metrics into existing data pipelines and tooling
Support and modify FPGA constraint and automation scripts as needed
Collaborate with internal and partner teams to enable reliable metric generation
Extend metric collection to additional FPGA platforms or legacy flows as required
Qualification
Required
Experience with FPGA vendor tools: Vivado (AMD) and Quartus (Altera)
Proficiency in Python and TCL scripting for automation and data extraction
Strong understanding of FPGA implementation flows, timing, and utilization
Experience with TCL scripting for Quartus
Familiarity with CI/CD-driven FPGA builds
Experience working with large or production FPGA infrastructures
Ability to extract design/tool data for automation and analytics
Preferred
Experience with TCL scripting for Quartus
Familiarity with CI/CD-driven FPGA builds
Experience working with large or production FPGA infrastructures
Benefits
Inclusive and diverse workplace culture.
Opportunities for professional growth and development.
Supportive team environment with a focus on collaboration.
Company
Scalence L.L.C.
In today’s dynamic and competitive market, success hinges on mastering three key areas: Data Intelligence, Business Resilience, and Digital Experience.
Funding
Current Stage
Late StageCompany data provided by crunchbase